From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: [PATCH v3 01/32] arm64: add explicit symbols to ESR_EL1 decoding Date: Mon, 8 Apr 2013 17:17:03 +0100 Message-ID: <1365437854-30214-2-git-send-email-marc.zyngier@arm.com> References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com> Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Cc: catalin.marinas@arm.com, will.deacon@arm.com To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Return-path: Received: from service87.mimecast.com ([91.220.42.44]:57411 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934579Ab3DHQRo (ORCPT ); Mon, 8 Apr 2013 12:17:44 -0400 In-Reply-To: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com> Sender: kvm-owner@vger.kernel.org List-ID: The ESR_EL1 decoding process is a bit cryptic, and KVM has also a need for the same constants. Add a new esr.h file containing the appropriate exception classes constants, and change entry.S to use it. Fix a small bug in the EL1 breakpoint check while we're at it. Signed-off-by: Marc Zyngier Cc: Catalin Marinas Cc: Will Deacon --- arch/arm64/include/asm/esr.h | 55 ++++++++++++++++++++++++++++++++++++++++= ++++ arch/arm64/kernel/entry.S | 53 +++++++++++++++++++++-------------------= -- 2 files changed, 82 insertions(+), 26 deletions(-) create mode 100644 arch/arm64/include/asm/esr.h diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h new file mode 100644 index 0000000..7883412 --- /dev/null +++ b/arch/arm64/include/asm/esr.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __ASM_ESR_H +#define __ASM_ESR_H + +#define ESR_EL1_EC_SHIFT=09(26) +#define ESR_EL1_IL=09=09(1U << 25) + +#define ESR_EL1_EC_UNKNOWN=09(0x00) +#define ESR_EL1_EC_WFI=09=09(0x01) +#define ESR_EL1_EC_CP15_32=09(0x03) +#define ESR_EL1_EC_CP15_64=09(0x04) +#define ESR_EL1_EC_CP14_MR=09(0x05) +#define ESR_EL1_EC_CP14_LS=09(0x06) +#define ESR_EL1_EC_FP_ASIMD=09(0x07) +#define ESR_EL1_EC_CP10_ID=09(0x08) +#define ESR_EL1_EC_CP14_64=09(0x0C) +#define ESR_EL1_EC_ILL_ISS=09(0x0E) +#define ESR_EL1_EC_SVC32=09(0x11) +#define ESR_EL1_EC_SVC64=09(0x15) +#define ESR_EL1_EC_SYS64=09(0x18) +#define ESR_EL1_EC_IABT_EL0=09(0x20) +#define ESR_EL1_EC_IABT_EL1=09(0x21) +#define ESR_EL1_EC_PC_ALIGN=09(0x22) +#define ESR_EL1_EC_DABT_EL0=09(0x24) +#define ESR_EL1_EC_DABT_EL1=09(0x25) +#define ESR_EL1_EC_SP_ALIGN=09(0x26) +#define ESR_EL1_EC_FP_EXC32=09(0x28) +#define ESR_EL1_EC_FP_EXC64=09(0x2C) +#define ESR_EL1_EC_SERRROR=09(0x2F) +#define ESR_EL1_EC_BREAKPT_EL0=09(0x30) +#define ESR_EL1_EC_BREAKPT_EL1=09(0x31) +#define ESR_EL1_EC_SOFTSTP_EL0=09(0x32) +#define ESR_EL1_EC_SOFTSTP_EL1=09(0x33) +#define ESR_EL1_EC_WATCHPT_EL0=09(0x34) +#define ESR_EL1_EC_WATCHPT_EL1=09(0x35) +#define ESR_EL1_EC_BKPT32=09(0x38) +#define ESR_EL1_EC_BRK64=09(0x3C) + +#endif /* __ASM_ESR_H */ diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 514d609..c7e0470 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -239,18 +240,18 @@ ENDPROC(el1_error_invalid) el1_sync: =09kernel_entry 1 =09mrs=09x1, esr_el1=09=09=09// read the syndrome register -=09lsr=09x24, x1, #26=09=09=09// exception class -=09cmp=09x24, #0x25=09=09=09// data abort in EL1 +=09lsr=09x24, x1, #ESR_EL1_EC_SHIFT=09// exception class +=09cmp=09x24, #ESR_EL1_EC_DABT_EL1=09// data abort in EL1 =09b.eq=09el1_da -=09cmp=09x24, #0x18=09=09=09// configurable trap +=09cmp=09x24, #ESR_EL1_EC_SYS64=09=09// configurable trap =09b.eq=09el1_undef -=09cmp=09x24, #0x26=09=09=09// stack alignment exception +=09cmp=09x24, #ESR_EL1_EC_SP_ALIGN=09// stack alignment exception =09b.eq=09el1_sp_pc -=09cmp=09x24, #0x22=09=09=09// pc alignment exception +=09cmp=09x24, #ESR_EL1_EC_PC_ALIGN=09// pc alignment exception =09b.eq=09el1_sp_pc -=09cmp=09x24, #0x00=09=09=09// unknown exception in EL1 +=09cmp=09x24, #ESR_EL1_EC_UNKNOWN=09// unknown exception in EL1 =09b.eq=09el1_undef -=09cmp=09x24, #0x30=09=09=09// debug exception in EL1 +=09cmp=09x24, #ESR_EL1_EC_BREAKPT_EL1=09// debug exception in EL1 =09b.ge=09el1_dbg =09b=09el1_inv el1_da: @@ -346,27 +347,27 @@ el1_preempt: el0_sync: =09kernel_entry 0 =09mrs=09x25, esr_el1=09=09=09// read the syndrome register -=09lsr=09x24, x25, #26=09=09=09// exception class -=09cmp=09x24, #0x15=09=09=09// SVC in 64-bit state +=09lsr=09x24, x25, #ESR_EL1_EC_SHIFT=09// exception class +=09cmp=09x24, #ESR_EL1_EC_SVC64=09=09// SVC in 64-bit state =09b.eq=09el0_svc =09adr=09lr, ret_from_exception -=09cmp=09x24, #0x24=09=09=09// data abort in EL0 +=09cmp=09x24, #ESR_EL1_EC_DABT_EL0=09// data abort in EL0 =09b.eq=09el0_da -=09cmp=09x24, #0x20=09=09=09// instruction abort in EL0 +=09cmp=09x24, #ESR_EL1_EC_IABT_EL0=09// instruction abort in EL0 =09b.eq=09el0_ia -=09cmp=09x24, #0x07=09=09=09// FP/ASIMD access +=09cmp=09x24, #ESR_EL1_EC_FP_ASIMD=09// FP/ASIMD access =09b.eq=09el0_fpsimd_acc -=09cmp=09x24, #0x2c=09=09=09// FP/ASIMD exception +=09cmp=09x24, #ESR_EL1_EC_FP_EXC64=09// FP/ASIMD exception =09b.eq=09el0_fpsimd_exc -=09cmp=09x24, #0x18=09=09=09// configurable trap +=09cmp=09x24, #ESR_EL1_EC_SYS64=09=09// configurable trap =09b.eq=09el0_undef -=09cmp=09x24, #0x26=09=09=09// stack alignment exception +=09cmp=09x24, #ESR_EL1_EC_SP_ALIGN=09// stack alignment exception =09b.eq=09el0_sp_pc -=09cmp=09x24, #0x22=09=09=09// pc alignment exception +=09cmp=09x24, #ESR_EL1_EC_PC_ALIGN=09// pc alignment exception =09b.eq=09el0_sp_pc -=09cmp=09x24, #0x00=09=09=09// unknown exception in EL0 +=09cmp=09x24, #ESR_EL1_EC_UNKNOWN=09// unknown exception in EL0 =09b.eq=09el0_undef -=09cmp=09x24, #0x30=09=09=09// debug exception in EL0 +=09cmp=09x24, #ESR_EL1_EC_BREAKPT_EL0=09// debug exception in EL0 =09b.ge=09el0_dbg =09b=09el0_inv =20 @@ -375,21 +376,21 @@ el0_sync: el0_sync_compat: =09kernel_entry 0, 32 =09mrs=09x25, esr_el1=09=09=09// read the syndrome register -=09lsr=09x24, x25, #26=09=09=09// exception class -=09cmp=09x24, #0x11=09=09=09// SVC in 32-bit state +=09lsr=09x24, x25, #ESR_EL1_EC_SHIFT=09// exception class +=09cmp=09x24, #ESR_EL1_EC_SVC32=09=09// SVC in 32-bit state =09b.eq=09el0_svc_compat =09adr=09lr, ret_from_exception -=09cmp=09x24, #0x24=09=09=09// data abort in EL0 +=09cmp=09x24, #ESR_EL1_EC_DABT_EL0=09// data abort in EL0 =09b.eq=09el0_da -=09cmp=09x24, #0x20=09=09=09// instruction abort in EL0 +=09cmp=09x24, #ESR_EL1_EC_IABT_EL0=09// instruction abort in EL0 =09b.eq=09el0_ia -=09cmp=09x24, #0x07=09=09=09// FP/ASIMD access +=09cmp=09x24, #ESR_EL1_EC_FP_ASIMD=09// FP/ASIMD access =09b.eq=09el0_fpsimd_acc -=09cmp=09x24, #0x28=09=09=09// FP/ASIMD exception +=09cmp=09x24, #ESR_EL1_EC_FP_EXC32=09// FP/ASIMD exception =09b.eq=09el0_fpsimd_exc -=09cmp=09x24, #0x00=09=09=09// unknown exception in EL0 +=09cmp=09x24, #ESR_EL1_EC_UNKNOWN=09// unknown exception in EL0 =09b.eq=09el0_undef -=09cmp=09x24, #0x30=09=09=09// debug exception in EL0 +=09cmp=09x24, #ESR_EL1_EC_BREAKPT_EL0=09// debug exception in EL0 =09b.ge=09el0_dbg =09b=09el0_inv el0_svc_compat: --=20 1.8.1.4