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From: Jun Nakajima <jun.nakajima@intel.com>
To: kvm@vger.kernel.org
Subject: [PATCH v2 04/13] nEPT: Define EPT-specific link_shadow_page()
Date: Mon,  6 May 2013 00:04:23 -0700	[thread overview]
Message-ID: <1367823872-25895-4-git-send-email-jun.nakajima@intel.com> (raw)
In-Reply-To: <1367823872-25895-3-git-send-email-jun.nakajima@intel.com>

Since link_shadow_page() is used by a routine in mmu.c, add an
EPT-specific link_shadow_page() in paging_tmp.h, rather than moving
it.

Signed-off-by: Nadav Har'El <nyh@il.ibm.com>
Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>
Signed-off-by: Xinhao Xu <xinhao.xu@intel.com>
---
 arch/x86/kvm/paging_tmpl.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index 5644f61..51dca23 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -461,6 +461,18 @@ static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
 	}
 }
 
+#if PTTYPE == PTTYPE_EPT
+static void FNAME(link_shadow_page)(u64 *sptep, struct kvm_mmu_page *sp)
+{
+	u64 spte;
+
+	spte = __pa(sp->spt) | VMX_EPT_READABLE_MASK | VMX_EPT_WRITABLE_MASK |
+		VMX_EPT_EXECUTABLE_MASK;
+
+	mmu_spte_set(sptep, spte);
+}
+#endif
+
 /*
  * Fetch a shadow pte for a specific level in the paging hierarchy.
  * If the guest tries to write a write-protected page, we need to
@@ -513,7 +525,11 @@ static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
 			goto out_gpte_changed;
 
 		if (sp)
+#if PTTYPE == PTTYPE_EPT
+			FNAME(link_shadow_page)(it.sptep, sp);
+#else
 			link_shadow_page(it.sptep, sp);
+#endif
 	}
 
 	for (;
@@ -533,7 +549,11 @@ static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
 
 		sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
 				      true, direct_access, it.sptep);
+#if PTTYPE == PTTYPE_EPT
+		FNAME(link_shadow_page)(it.sptep, sp);
+#else
 		link_shadow_page(it.sptep, sp);
+#endif
 	}
 
 	clear_sp_write_flooding_count(it.sptep);
-- 
1.8.1.2


  reply	other threads:[~2013-05-06  7:04 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-05-06  7:04 [PATCH v2 01/13] nEPT: Support LOAD_IA32_EFER entry/exit controls for L1 Jun Nakajima
2013-05-06  7:04 ` [PATCH v2 02/13] nEPT: Move gpte_access() and prefetch_invalid_gpte() to paging_tmpl.h Jun Nakajima
2013-05-06  7:04   ` [PATCH v2 03/13] nEPT: Add EPT tables support " Jun Nakajima
2013-05-06  7:04     ` Jun Nakajima [this message]
2013-05-06  7:04       ` [PATCH v2 05/13] nEPT: MMU context for nested EPT Jun Nakajima
2013-05-06  7:04         ` [PATCH v2 06/13] nEPT: Fix cr3 handling in nested exit and entry Jun Nakajima
2013-05-06  7:04           ` [PATCH v2 07/13] nEPT: Fix wrong test in kvm_set_cr3 Jun Nakajima
2013-05-06  7:04             ` [PATCH v2 08/13] nEPT: Some additional comments Jun Nakajima
2013-05-06  7:04               ` [PATCH v2 09/13] nEPT: Advertise EPT to L1 Jun Nakajima
2013-05-06  7:04                 ` [PATCH v2 10/13] nEPT: Nested INVEPT Jun Nakajima
2013-05-06  7:04                   ` [PATCH v2 11/13] nEPT: Miscelleneous cleanups Jun Nakajima
2013-05-06  7:04                     ` [PATCH v2 12/13] nEPT: Move is_rsvd_bits_set() to paging_tmpl.h Jun Nakajima
2013-05-06  7:04                       ` [PATCH v2 13/13] nEPT: Inject EPT violation/misconfigration Jun Nakajima
2013-05-06  7:13 ` [PATCH v2 01/13] nEPT: Support LOAD_IA32_EFER entry/exit controls for L1 Jan Kiszka

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