From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: [PATCH v4 03/32] arm64: KVM: EL2 register definitions Date: Tue, 14 May 2013 15:13:31 +0100 Message-ID: <1368540840-26750-4-git-send-email-marc.zyngier@arm.com> References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com> Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Cc: catalin.marinas@arm.com, will.deacon@arm.com, pbonzini@redhat.com, gleb@redhat.com, Christopher Covington To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Return-path: Received: from service87.mimecast.com ([91.220.42.44]:48144 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754865Ab3ENOOX (ORCPT ); Tue, 14 May 2013 10:14:23 -0400 In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com> Sender: kvm-owner@vger.kernel.org List-ID: Define all the useful bitfields for EL2 registers. Reviewed-by: Christopher Covington Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_arm.h | 245 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 245 insertions(+) create mode 100644 arch/arm64/include/asm/kvm_arm.h diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h new file mode 100644 index 0000000..a5f28e2 --- /dev/null +++ b/arch/arm64/include/asm/kvm_arm.h @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2012,2013 - ARM Ltd + * Author: Marc Zyngier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __ARM64_KVM_ARM_H__ +#define __ARM64_KVM_ARM_H__ + +#include + +/* Hyp Configuration Register (HCR) bits */ +#define HCR_ID=09=09(UL(1) << 33) +#define HCR_CD=09=09(UL(1) << 32) +#define HCR_RW_SHIFT=0931 +#define HCR_RW=09=09(UL(1) << HCR_RW_SHIFT) +#define HCR_TRVM=09(UL(1) << 30) +#define HCR_HCD=09=09(UL(1) << 29) +#define HCR_TDZ=09=09(UL(1) << 28) +#define HCR_TGE=09=09(UL(1) << 27) +#define HCR_TVM=09=09(UL(1) << 26) +#define HCR_TTLB=09(UL(1) << 25) +#define HCR_TPU=09=09(UL(1) << 24) +#define HCR_TPC=09=09(UL(1) << 23) +#define HCR_TSW=09=09(UL(1) << 22) +#define HCR_TAC=09=09(UL(1) << 21) +#define HCR_TIDCP=09(UL(1) << 20) +#define HCR_TSC=09=09(UL(1) << 19) +#define HCR_TID3=09(UL(1) << 18) +#define HCR_TID2=09(UL(1) << 17) +#define HCR_TID1=09(UL(1) << 16) +#define HCR_TID0=09(UL(1) << 15) +#define HCR_TWE=09=09(UL(1) << 14) +#define HCR_TWI=09=09(UL(1) << 13) +#define HCR_DC=09=09(UL(1) << 12) +#define HCR_BSU=09=09(3 << 10) +#define HCR_BSU_IS=09(UL(1) << 10) +#define HCR_FB=09=09(UL(1) << 9) +#define HCR_VA=09=09(UL(1) << 8) +#define HCR_VI=09=09(UL(1) << 7) +#define HCR_VF=09=09(UL(1) << 6) +#define HCR_AMO=09=09(UL(1) << 5) +#define HCR_IMO=09=09(UL(1) << 4) +#define HCR_FMO=09=09(UL(1) << 3) +#define HCR_PTW=09=09(UL(1) << 2) +#define HCR_SWIO=09(UL(1) << 1) +#define HCR_VM=09=09(UL(1) << 0) + +/* + * The bits we set in HCR: + * RW:=09=0964bit by default, can be overriden for 32bit VMs + * TAC:=09=09Trap ACTLR + * TSC:=09=09Trap SMC + * TSW:=09=09Trap cache operations by set/way + * TWI:=09=09Trap WFI + * TIDCP:=09Trap L2CTLR/L2ECTLR + * BSU_IS:=09Upgrade barriers to the inner shareable domain + * FB:=09=09Force broadcast of all maintainance operations + * AMO:=09=09Override CPSR.A and enable signaling with VA + * IMO:=09=09Override CPSR.I and enable signaling with VI + * FMO:=09=09Override CPSR.F and enable signaling with VF + * SWIO:=09Turn set/way invalidates into set/way clean+invalidate + */ +#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS= | \ +=09=09=09 HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \ +=09=09=09 HCR_SWIO | HCR_TIDCP | HCR_RW) +#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF) + +/* Hyp System Control Register (SCTLR_EL2) bits */ +#define SCTLR_EL2_EE=09(1 << 25) +#define SCTLR_EL2_WXN=09(1 << 19) +#define SCTLR_EL2_I=09(1 << 12) +#define SCTLR_EL2_SA=09(1 << 3) +#define SCTLR_EL2_C=09(1 << 2) +#define SCTLR_EL2_A=09(1 << 1) +#define SCTLR_EL2_M=091 +#define SCTLR_EL2_FLAGS=09(SCTLR_EL2_M | SCTLR_EL2_A | SCTLR_EL2_C |=09\ +=09=09=09 SCTLR_EL2_SA | SCTLR_EL2_I) + +/* TCR_EL2 Registers bits */ +#define TCR_EL2_TBI=09(1 << 20) +#define TCR_EL2_PS=09(7 << 16) +#define TCR_EL2_PS_40B=09(2 << 16) +#define TCR_EL2_TG0=09(1 << 14) +#define TCR_EL2_SH0=09(3 << 12) +#define TCR_EL2_ORGN0=09(3 << 10) +#define TCR_EL2_IRGN0=09(3 << 8) +#define TCR_EL2_T0SZ=090x3f +#define TCR_EL2_MASK=09(TCR_EL2_TG0 | TCR_EL2_SH0 | \ +=09=09=09 TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ) + +#define TCR_EL2_FLAGS=09(TCR_EL2_PS_40B) + +/* VTCR_EL2 Registers bits */ +#define VTCR_EL2_PS_MASK=09(7 << 16) +#define VTCR_EL2_PS_40B=09=09(2 << 16) +#define VTCR_EL2_TG0_MASK=09(1 << 14) +#define VTCR_EL2_TG0_4K=09=09(0 << 14) +#define VTCR_EL2_TG0_64K=09(1 << 14) +#define VTCR_EL2_SH0_MASK=09(3 << 12) +#define VTCR_EL2_SH0_INNER=09(3 << 12) +#define VTCR_EL2_ORGN0_MASK=09(3 << 10) +#define VTCR_EL2_ORGN0_WBWA=09(1 << 10) +#define VTCR_EL2_IRGN0_MASK=09(3 << 8) +#define VTCR_EL2_IRGN0_WBWA=09(1 << 8) +#define VTCR_EL2_SL0_MASK=09(3 << 6) +#define VTCR_EL2_SL0_LVL1=09(1 << 6) +#define VTCR_EL2_T0SZ_MASK=090x3f +#define VTCR_EL2_T0SZ_40B=0924 + +#ifdef CONFIG_ARM64_64K_PAGES +/* + * Stage2 translation configuration: + * 40bits output (PS =3D 2) + * 40bits input (T0SZ =3D 24) + * 64kB pages (TG0 =3D 1) + * 2 level page tables (SL =3D 1) + */ +#define VTCR_EL2_FLAGS=09=09(VTCR_EL2_PS_40B | VTCR_EL2_TG0_64K | \ +=09=09=09=09 VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ +=09=09=09=09 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \ +=09=09=09=09 VTCR_EL2_T0SZ_40B) +#define VTTBR_X=09=09(38 - VTCR_EL2_T0SZ_40B) +#else +/* + * Stage2 translation configuration: + * 40bits output (PS =3D 2) + * 40bits input (T0SZ =3D 24) + * 4kB pages (TG0 =3D 0) + * 3 level page tables (SL =3D 1) + */ +#define VTCR_EL2_FLAGS=09=09(VTCR_EL2_PS_40B | VTCR_EL2_TG0_4K | \ +=09=09=09=09 VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ +=09=09=09=09 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \ +=09=09=09=09 VTCR_EL2_T0SZ_40B) +#define VTTBR_X=09=09(37 - VTCR_EL2_T0SZ_40B) +#endif + +#define VTTBR_BADDR_SHIFT (VTTBR_X - 1) +#define VTTBR_BADDR_MASK (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_S= HIFT) +#define VTTBR_VMID_SHIFT (48LLU) +#define VTTBR_VMID_MASK=09 (0xffLLU << VTTBR_VMID_SHIFT) + +/* Hyp System Trap Register */ +#define HSTR_EL2_TTEE=09(1 << 16) +#define HSTR_EL2_T(x)=09(1 << x) + +/* Hyp Coprocessor Trap Register */ +#define CPTR_EL2_TCPAC=09(1 << 31) +#define CPTR_EL2_TTA=09(1 << 20) +#define CPTR_EL2_TFP=09(1 << 10) + +/* Hyp Debug Configuration Register bits */ +#define MDCR_EL2_TDRA=09=09(1 << 11) +#define MDCR_EL2_TDOSA=09=09(1 << 10) +#define MDCR_EL2_TDA=09=09(1 << 9) +#define MDCR_EL2_TDE=09=09(1 << 8) +#define MDCR_EL2_HPME=09=09(1 << 7) +#define MDCR_EL2_TPM=09=09(1 << 6) +#define MDCR_EL2_TPMCR=09=09(1 << 5) +#define MDCR_EL2_HPMN_MASK=09(0x1F) + +/* Exception Syndrome Register (ESR) bits */ +#define ESR_EL2_EC_SHIFT=09(26) +#define ESR_EL2_EC=09=09(0x3fU << ESR_EL2_EC_SHIFT) +#define ESR_EL2_IL=09=09(1U << 25) +#define ESR_EL2_ISS=09=09(ESR_EL2_IL - 1) +#define ESR_EL2_ISV_SHIFT=09(24) +#define ESR_EL2_ISV=09=09(1U << ESR_EL2_ISV_SHIFT) +#define ESR_EL2_SAS_SHIFT=09(22) +#define ESR_EL2_SAS=09=09(3U << ESR_EL2_SAS_SHIFT) +#define ESR_EL2_SSE=09=09(1 << 21) +#define ESR_EL2_SRT_SHIFT=09(16) +#define ESR_EL2_SRT_MASK=09(0x1f << ESR_EL2_SRT_SHIFT) +#define ESR_EL2_SF =09=09(1 << 15) +#define ESR_EL2_AR =09=09(1 << 14) +#define ESR_EL2_EA =09=09(1 << 9) +#define ESR_EL2_CM =09=09(1 << 8) +#define ESR_EL2_S1PTW =09=09(1 << 7) +#define ESR_EL2_WNR=09=09(1 << 6) +#define ESR_EL2_FSC=09=09(0x3f) +#define ESR_EL2_FSC_TYPE=09(0x3c) + +#define ESR_EL2_CV_SHIFT=09(24) +#define ESR_EL2_CV=09=09(1U << ESR_EL2_CV_SHIFT) +#define ESR_EL2_COND_SHIFT=09(20) +#define ESR_EL2_COND=09=09(0xfU << ESR_EL2_COND_SHIFT) + + +#define FSC_FAULT=09(0x04) +#define FSC_PERM=09(0x0c) + +/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ +#define HPFAR_MASK=09(~0xFUL) + +#define ESR_EL2_EC_UNKNOWN=09(0x00) +#define ESR_EL2_EC_WFI=09=09(0x01) +#define ESR_EL2_EC_CP15_32=09(0x03) +#define ESR_EL2_EC_CP15_64=09(0x04) +#define ESR_EL2_EC_CP14_MR=09(0x05) +#define ESR_EL2_EC_CP14_LS=09(0x06) +#define ESR_EL2_EC_FP_ASIMD=09(0x07) +#define ESR_EL2_EC_CP10_ID=09(0x08) +#define ESR_EL2_EC_CP14_64=09(0x0C) +#define ESR_EL2_EC_ILL_ISS=09(0x0E) +#define ESR_EL2_EC_SVC32=09(0x11) +#define ESR_EL2_EC_HVC32=09(0x12) +#define ESR_EL2_EC_SMC32=09(0x13) +#define ESR_EL2_EC_SVC64=09(0x15) +#define ESR_EL2_EC_HVC64=09(0x16) +#define ESR_EL2_EC_SMC64=09(0x17) +#define ESR_EL2_EC_SYS64=09(0x18) +#define ESR_EL2_EC_IABT=09=09(0x20) +#define ESR_EL2_EC_IABT_HYP=09(0x21) +#define ESR_EL2_EC_PC_ALIGN=09(0x22) +#define ESR_EL2_EC_DABT=09=09(0x24) +#define ESR_EL2_EC_DABT_HYP=09(0x25) +#define ESR_EL2_EC_SP_ALIGN=09(0x26) +#define ESR_EL2_EC_FP_EXC32=09(0x28) +#define ESR_EL2_EC_FP_EXC64=09(0x2C) +#define ESR_EL2_EC_SERRROR=09(0x2F) +#define ESR_EL2_EC_BREAKPT=09(0x30) +#define ESR_EL2_EC_BREAKPT_HYP=09(0x31) +#define ESR_EL2_EC_SOFTSTP=09(0x32) +#define ESR_EL2_EC_SOFTSTP_HYP=09(0x33) +#define ESR_EL2_EC_WATCHPT=09(0x34) +#define ESR_EL2_EC_WATCHPT_HYP=09(0x35) +#define ESR_EL2_EC_BKPT32=09(0x38) +#define ESR_EL2_EC_VECTOR32=09(0x3A) +#define ESR_EL2_EC_BRK64=09(0x3C) + +#define ESR_EL2_EC_xABT_xFSR_EXTABT=090x10 + +#endif /* __ARM64_KVM_ARM_H__ */ --=20 1.8.2.3