From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andreas Herrmann Subject: [PATCH 04/15] MIPS: Don't use RI/XI with 32-bit kernels on 64-bit CPUs. Date: Tue, 20 May 2014 16:47:05 +0200 Message-ID: <1400597236-11352-5-git-send-email-andreas.herrmann@caviumnetworks.com> References: <1400597236-11352-1-git-send-email-andreas.herrmann@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain Cc: David Daney , Andreas Herrmann , Ralf Baechle , James Hogan , , David Daney To: Return-path: Received: from mail-bl2lp0212.outbound.protection.outlook.com ([207.46.163.212]:7450 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751907AbaETOsv (ORCPT ); Tue, 20 May 2014 10:48:51 -0400 In-Reply-To: <1400597236-11352-1-git-send-email-andreas.herrmann@caviumnetworks.com> Sender: kvm-owner@vger.kernel.org List-ID: From: David Daney The TLB handlers cannot handle this case, so disable it for now. Signed-off-by: David Daney Signed-off-by: Andreas Herrmann --- arch/mips/include/asm/cpu-features.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index f56cc97..01486eb 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -110,9 +110,15 @@ #ifndef cpu_has_smartmips #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif + #ifndef cpu_has_rixi -#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) +# ifdef CONFIG_64BIT +# define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) +# else /* CONFIG_32BIT */ +# define cpu_has_rixi ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits) +# endif #endif + #ifndef cpu_has_mmips # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) @@ -120,6 +126,7 @@ # define cpu_has_mmips 0 # endif #endif + #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) #endif -- 1.7.9.5