[PATCH 1/3] x86: apic: Look up MAXPHYADDR on CPUID correctly

[Eduardo Habkost <ehabkost@redhat.com>]

When the CPUID xlevel on QEMU is < 0x80000008, we get the following:

    $ ./x86-run x86/apic.flat -smp 2 -cpu qemu64,xlevel=0x80000007
    [...]
    FAIL: apicbase: reserved physaddr bits

That happens because CPUID[0x80000008].EAX won't have the expected data
if xlevel < 0x80000008.

When the CPUID physical address bits information is not available on CPUID,
assume it is 36, as documented on Intel SDM, Volume 3A, section
10.4.4 "Local APIC Status and Location":

> Bits 0 through 7, bits 9 and 10, and bits MAXPHYADDR[1] through 63 in the
> IA32_APIC_BASE MSR are reserved.
>
> [1] The MAXPHYADDR is 36 bits for processors that do not support CPUID
> leaf 80000008H, or indicated by CPUID.80000008H:EAX[bits 7:0] for
> processors that support CPUID leaf 80000008H."

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 lib/x86/processor.h | 8 ++++++++
 x86/apic.c          | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/lib/x86/processor.h b/lib/x86/processor.h
index f5f1c82..d4e295b 100644
--- a/lib/x86/processor.h
+++ b/lib/x86/processor.h
@@ -294,6 +294,14 @@ static inline struct cpuid cpuid(u32 function)
     return cpuid_indexed(function, 0);
 }
 
+static inline u8 cpuid_maxphyaddr(void)
+{
+    if (cpuid(0x80000000).a < 0x80000008)
+        return 36;
+    return cpuid(0x80000008).a & 0xff;
+}
+
+
 static inline void pause(void)
 {
     asm volatile ("pause");
diff --git a/x86/apic.c b/x86/apic.c
index 3f463a5..2619d85 100644
--- a/x86/apic.c
+++ b/x86/apic.c
@@ -124,7 +124,7 @@ static void test_apicbase(void)
     report("relocate apic",
            *(volatile u32 *)(ALTERNATE_APIC_BASE + APIC_LVR) == lvr);
 
-    value = orig_apicbase | (1UL << (cpuid(0x80000008).a & 0xff));
+    value = orig_apicbase | (1UL << cpuid_maxphyaddr());
     report("apicbase: reserved physaddr bits",
            test_for_exception(GP_VECTOR, do_write_apicbase, &value));
 
-- 
1.9.3