From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wincy Van Subject: [PATCH resend v5 0/6] KVM: nVMX: Enable nested apicv support Date: Tue, 3 Feb 2015 23:46:55 +0800 Message-ID: <1422978415-2006-1-git-send-email-fanwenyi0529@gmail.com> Cc: wanpeng.li@linux.intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, jan.kiszka@web.de To: pbonzini@redhat.com, gleb@kernel.org, yang.z.zhang@intel.com, fanwenyi0529@gmail.com Return-path: Received: from smtpbg302.qq.com ([184.105.206.27]:37819 "EHLO smtpbg302.qq.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753653AbbBCP7h (ORCPT ); Tue, 3 Feb 2015 10:59:37 -0500 Sender: kvm-owner@vger.kernel.org List-ID: v1 ---> v2: Use spin lock to ensure vmcs12 is safe when doing nested posted interrupt delivery. v2 ---> v3: 1. Add a new field in nested_vmx to avoid the spin lock in v2. 2. Drop send eoi to L1 when doing nested interrupt delivery. 3. Use hardware MSR bitmap to enable nested virtualize x2apic mode. v3 ---> v4: 1. Optimize nested msr bitmap merging. 2. Allocate nested msr bitmap only when nested == 1. 3. Inline the nested vmx control checking functions. v4 ---> v5: 1. Move EXIT_REASON_APIC_WRITE to the apic register virtualization patch. 2. Accomplish nested posted interrupts manually if they are not recognized by hardware. Wincy Van (6): KVM: nVMX: Use hardware MSR bitmap KVM: nVMX: Enable nested virtualize x2apic mode KVM: nVMX: Make nested control MSRs per-cpu KVM: nVMX: Enable nested apic register virtualization KVM: nVMX: Enable nested virtual interrupt delivery KVM: nVMX: Enable nested posted interrupt processing arch/x86/kvm/lapic.c | 13 +- arch/x86/kvm/lapic.h | 1 + arch/x86/kvm/vmx.c | 647 ++++++++++++++++++++++++++++++++++++++++++-------- 3 files changed, 557 insertions(+), 104 deletions(-)