From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Feiner Subject: [kvm-unit-tests PATCH] x86: vmx: fix definition of X86_CR4_VMXE Date: Mon, 22 Feb 2016 15:40:36 -0800 Message-ID: <1456184436-31168-1-git-send-email-pfeiner@google.com> Cc: pfeiner@google.com To: kvm@vger.kernel.org, drjones@redhat.com, pbonzini@redhat.com Return-path: Received: from mail-pf0-f170.google.com ([209.85.192.170]:34172 "EHLO mail-pf0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756407AbcBVXkm (ORCPT ); Mon, 22 Feb 2016 18:40:42 -0500 Received: by mail-pf0-f170.google.com with SMTP id x65so100688879pfb.1 for ; Mon, 22 Feb 2016 15:40:41 -0800 (PST) Sender: kvm-owner@vger.kernel.org List-ID: Was defined as 0x1 when it should have been 0x2000 (13th bit of CR4). See Intel manual 23.7. 0x1 is the VME 'Virtual-8086 Mode Extensions' bit, which the vmx tests don't exercise. The correct bit was being set thanks to IA32_VMX_CR4_FIXED{0,1} MSRs forcing it. I hacked the test setup to forcibly un-set the bit and observed the correct #UD VMXON behavior. Adding a test to verify the #UD behavior is follow-up work. Signed-off-by: Peter Feiner --- lib/x86/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/x86/processor.h b/lib/x86/processor.h index 95cea1a..dff1689 100644 --- a/lib/x86/processor.h +++ b/lib/x86/processor.h @@ -21,7 +21,7 @@ #define X86_CR0_WP 0x00010000 #define X86_CR0_AM 0x00040000 #define X86_CR0_PG 0x80000000 -#define X86_CR4_VMXE 0x00000001 +#define X86_CR4_VMXE 0x00002000 #define X86_CR4_TSD 0x00000004 #define X86_CR4_DE 0x00000008 #define X86_CR4_PSE 0x00000010 -- 2.7.0.rc3.207.g0ac5344