From: Sascha Bischoff <Sascha.Bischoff@arm.com>
To: Andre Przywara <Andre.Przywara@arm.com>,
"will@kernel.org" <will@kernel.org>,
"julien.thierry.kdev@gmail.com" <julien.thierry.kdev@gmail.com>
Cc: "maz@kernel.org" <maz@kernel.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
Alexandru Elisei <Alexandru.Elisei@arm.com>, nd <nd@arm.com>
Subject: Re: [PATCH kvmtool v7 6/6] arm64: Handle virtio endianness reset when running nested
Date: Tue, 7 Apr 2026 13:49:24 +0000 [thread overview]
Message-ID: <14785aa3b087d6b38beba26c85048fb26bf486bb.camel@arm.com> (raw)
In-Reply-To: <20260323164717.2571585-7-andre.przywara@arm.com>
On Mon, 2026-03-23 at 17:47 +0100, Andre Przywara wrote:
> From: Marc Zyngier <maz@kernel.org>
>
> When running an EL2 guest, we need to make sure we don't sample
> SCTLR_EL1 to work out the virtio endianness, as this is likely
> to be a bit random.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This also looks good to me now.
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Thanks,
Sascha
> ---
> arm64/include/kvm/kvm-cpu-arch.h | 5 +--
> arm64/kvm-cpu.c | 58 ++++++++++++++++++++++++++----
> --
> 2 files changed, 51 insertions(+), 12 deletions(-)
>
> diff --git a/arm64/include/kvm/kvm-cpu-arch.h
> b/arm64/include/kvm/kvm-cpu-arch.h
> index 1af394aa..88cef813 100644
> --- a/arm64/include/kvm/kvm-cpu-arch.h
> +++ b/arm64/include/kvm/kvm-cpu-arch.h
> @@ -10,8 +10,9 @@
> #define ARM_MPIDR_HWID_BITMASK 0xFF00FFFFFFUL
> #define ARM_CPU_ID 3, 0, 0, 0
> #define ARM_CPU_ID_MPIDR 5
> -#define ARM_CPU_CTRL 3, 0, 1, 0
> -#define ARM_CPU_CTRL_SCTLR_EL1 0
> +#define SYS_SCTLR_EL1 3, 0, 1, 0, 0
> +#define SYS_SCTLR_EL2 3, 4, 1, 0, 0
> +#define SYS_HCR_EL2 3, 4, 1, 1, 0
>
> struct kvm_cpu {
> pthread_t thread;
> diff --git a/arm64/kvm-cpu.c b/arm64/kvm-cpu.c
> index 5e4f3a7d..7b012e7a 100644
> --- a/arm64/kvm-cpu.c
> +++ b/arm64/kvm-cpu.c
> @@ -12,6 +12,8 @@
>
> #define SCTLR_EL1_E0E_MASK (1 << 24)
> #define SCTLR_EL1_EE_MASK (1 << 25)
> +#define HCR_EL2_TGE (1UL << 27)
> +#define HCR_EL2_E2H (1UL << 34)
>
> static int debug_fd;
>
> @@ -408,7 +410,8 @@ int kvm_cpu__get_endianness(struct kvm_cpu *vcpu)
> {
> struct kvm_one_reg reg;
> u64 psr;
> - u64 sctlr;
> + u64 sctlr, bit;
> + u64 hcr = 0;
>
> /*
> * Quoting the definition given by Peter Maydell:
> @@ -419,8 +422,9 @@ int kvm_cpu__get_endianness(struct kvm_cpu *vcpu)
> * We first check for an AArch32 guest: its endianness can
> * change when using SETEND, which affects the CPSR.E bit.
> *
> - * If we're AArch64, use SCTLR_EL1.E0E if access comes from
> - * EL0, and SCTLR_EL1.EE if access comes from EL1.
> + * If we're AArch64, determine which SCTLR register to use,
> + * depending on NV being used or not. Then use either the
> E0E
> + * bit for EL0, or the EE bit for EL1/EL2.
> */
> reg.id = ARM64_CORE_REG(regs.pstate);
> reg.addr = (u64)&psr;
> @@ -430,16 +434,50 @@ int kvm_cpu__get_endianness(struct kvm_cpu
> *vcpu)
> if (psr & PSR_MODE32_BIT)
> return (psr & COMPAT_PSR_E_BIT) ? VIRTIO_ENDIAN_BE :
> VIRTIO_ENDIAN_LE;
>
> - reg.id = ARM64_SYS_REG(ARM_CPU_CTRL,
> ARM_CPU_CTRL_SCTLR_EL1);
> + if (vcpu->kvm->cfg.arch.nested_virt) {
> + reg.id = ARM64_SYS_REG(SYS_HCR_EL2);
> + reg.addr = (u64)&hcr;
> + if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0)
> + die("KVM_GET_ONE_REG failed (HCR_EL2)");
> + }
> +
> + switch (psr & PSR_MODE_MASK) {
> + case PSR_MODE_EL0t:
> + switch (hcr & (HCR_EL2_E2H | HCR_EL2_TGE)) {
> + case HCR_EL2_E2H | HCR_EL2_TGE: /* EL2&0 */
> + reg.id = ARM64_SYS_REG(SYS_SCTLR_EL2);
> + bit = SCTLR_EL1_E0E_MASK;
> + break;
> + case HCR_EL2_TGE: /* EL2 */
> + reg.id = ARM64_SYS_REG(SYS_SCTLR_EL2);
> + bit = SCTLR_EL1_EE_MASK;
> + break;
> + case HCR_EL2_E2H: /* EL1&0 (VHE) */
> + default: /* EL1&0 (!VHE) */
> + reg.id = ARM64_SYS_REG(SYS_SCTLR_EL1);
> + bit = SCTLR_EL1_E0E_MASK;
> + break;
> + }
> + break;
> + case PSR_MODE_EL1t:
> + case PSR_MODE_EL1h:
> + reg.id = ARM64_SYS_REG(SYS_SCTLR_EL1);
> + bit = SCTLR_EL1_EE_MASK;
> + break;
> + case PSR_MODE_EL2t:
> + case PSR_MODE_EL2h:
> + reg.id = ARM64_SYS_REG(SYS_SCTLR_EL2);
> + bit = SCTLR_EL1_EE_MASK;
> + break;
> + default:
> + die("What's that mode???\n");
> + }
> +
> reg.addr = (u64)&sctlr;
> if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0)
> - die("KVM_GET_ONE_REG failed (SCTLR_EL1)");
> + die("KVM_GET_ONE_REG failed (SCTLR_ELx)");
>
> - if ((psr & PSR_MODE_MASK) == PSR_MODE_EL0t)
> - sctlr &= SCTLR_EL1_E0E_MASK;
> - else
> - sctlr &= SCTLR_EL1_EE_MASK;
> - return sctlr ? VIRTIO_ENDIAN_BE : VIRTIO_ENDIAN_LE;
> + return (sctlr & bit) ? VIRTIO_ENDIAN_BE : VIRTIO_ENDIAN_LE;
> }
>
> void kvm_cpu__show_code(struct kvm_cpu *vcpu)
prev parent reply other threads:[~2026-04-07 13:50 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-23 16:47 [PATCH kvmtool v7 0/6] arm64: Nested virtualization support Andre Przywara
2026-03-23 16:47 ` [PATCH kvmtool v7 1/6] arm64: Initial nested virt support Andre Przywara
2026-03-23 16:47 ` [PATCH kvmtool v7 2/6] arm64: nested: Add support for setting maintenance IRQ Andre Przywara
2026-04-07 13:47 ` Sascha Bischoff
2026-03-23 16:47 ` [PATCH kvmtool v7 3/6] arm64: Add counter offset control Andre Przywara
2026-03-23 16:47 ` [PATCH kvmtool v7 4/6] arm64: Add FEAT_E2H0 support Andre Przywara
2026-03-23 16:47 ` [PATCH kvmtool v7 5/6] arm64: Generate HYP timer interrupt specifiers Andre Przywara
2026-03-23 16:47 ` [PATCH kvmtool v7 6/6] arm64: Handle virtio endianness reset when running nested Andre Przywara
2026-04-07 13:49 ` Sascha Bischoff [this message]
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