From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Xu Subject: [PATCH v3 06/25] pci: Rework pci_bar_addr() Date: Mon, 14 Nov 2016 17:19:02 -0500 Message-ID: <1479161961-20304-7-git-send-email-peterx@redhat.com> References: <1479161961-20304-1-git-send-email-peterx@redhat.com> Cc: drjones@redhat.com, agordeev@redhat.com, jan.kiszka@web.de, rkrcmar@redhat.com, pbonzini@redhat.com, peterx@redhat.com To: kvm@vger.kernel.org Return-path: Received: from mx1.redhat.com ([209.132.183.28]:41030 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964844AbcKNWTb (ORCPT ); Mon, 14 Nov 2016 17:19:31 -0500 In-Reply-To: <1479161961-20304-1-git-send-email-peterx@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: From: Alexander Gordeev This update makes pci_bar_addr() interface 64 bit BARs aware and introduces a concept of PCI address translation. An architecutre should implement pci_translate_addr() interface in order to provide mapping between PCI bus address and CPU physical address. Cc: Thomas Huth Cc: Andrew Jones Cc: Peter Xu Reviewed-by: Andrew Jones Reviewed-by: Thomas Huth Signed-off-by: Alexander Gordeev --- lib/pci.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++---- lib/pci.h | 17 ++++++++++++- lib/x86/asm/pci.h | 6 +++++ 3 files changed, 90 insertions(+), 6 deletions(-) diff --git a/lib/pci.c b/lib/pci.c index ce481bb..3bf45fb 100644 --- a/lib/pci.c +++ b/lib/pci.c @@ -21,19 +21,71 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id) return PCIDEVADDR_INVALID; } +static uint32_t pci_bar_mask(uint32_t bar) +{ + return (bar & PCI_BASE_ADDRESS_SPACE_IO) ? + PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK; +} + static uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num) { return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4); } -unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num) +phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num) { uint32_t bar = pci_bar_get(dev, bar_num); + uint32_t mask = pci_bar_mask(bar); + uint64_t addr = bar & mask; - if (bar & PCI_BASE_ADDRESS_SPACE_IO) - return bar & PCI_BASE_ADDRESS_IO_MASK; - else - return bar & PCI_BASE_ADDRESS_MEM_MASK; + if (pci_bar_is64(dev, bar_num)) + addr |= (uint64_t)pci_bar_get(dev, bar_num + 1) << 32; + + return pci_translate_addr(dev, addr); +} + +/* + * To determine the amount of address space needed by a PCI device, + * one must save the original value of the BAR, write a value of + * all 1's to the register, and then read it back. The amount of + * memory can be then determined by masking the information bits, + * performing a bitwise NOT, and incrementing the value by 1. + * + * The following pci_bar_size_helper() and pci_bar_size() functions + * implement the algorithm. + */ +static uint32_t pci_bar_size_helper(pcidevaddr_t dev, int bar_num) +{ + int off = PCI_BASE_ADDRESS_0 + bar_num * 4; + uint32_t bar, val; + + bar = pci_config_readl(dev, off); + pci_config_writel(dev, off, ~0u); + val = pci_config_readl(dev, off); + pci_config_writel(dev, off, bar); + + return val; +} + +phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num) +{ + uint32_t bar, size; + + size = pci_bar_size_helper(dev, bar_num); + if (!size) + return 0; + + bar = pci_bar_get(dev, bar_num); + size &= pci_bar_mask(bar); + + if (pci_bar_is64(dev, bar_num)) { + phys_addr_t size64 = pci_bar_size_helper(dev, bar_num + 1); + size64 = (size64 << 32) | size; + + return ~size64 + 1; + } else { + return ~size + 1; + } } bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num) @@ -47,3 +99,14 @@ bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num) { return pci_bar_get(dev, bar_num); } + +bool pci_bar_is64(pcidevaddr_t dev, int bar_num) +{ + uint32_t bar = pci_bar_get(dev, bar_num); + + if (bar & PCI_BASE_ADDRESS_SPACE_IO) + return false; + + return (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == + PCI_BASE_ADDRESS_MEM_TYPE_64; +} diff --git a/lib/pci.h b/lib/pci.h index 066fac7..8eec236 100644 --- a/lib/pci.h +++ b/lib/pci.h @@ -16,7 +16,22 @@ enum { }; extern pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id); -extern unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num); + +/* + * @bar_num in all BAR access functions below is the index of the 32-bit + * register starting from the PCI_BASE_ADDRESS_0 offset. + * + * In cases where the BAR size is 64-bit, a caller should still provide + * @bar_num in terms of 32-bit words. For example, if a device has a 64-bit + * BAR#0 and a 32-bit BAR#1, then caller should provide 2 to address BAR#1, + * not 1. + * + * It is expected the caller is aware of the device BAR layout and never + * tries to address the middle of a 64-bit register. + */ +extern phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num); +extern phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num); +extern bool pci_bar_is64(pcidevaddr_t dev, int bar_num); extern bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num); extern bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num); diff --git a/lib/x86/asm/pci.h b/lib/x86/asm/pci.h index 4862ab5..c937e5c 100644 --- a/lib/x86/asm/pci.h +++ b/lib/x86/asm/pci.h @@ -50,4 +50,10 @@ static inline void pci_config_writel(pcidevaddr_t dev, uint8_t reg, outl(val, 0xCFC); } +static inline +phys_addr_t pci_translate_addr(pcidevaddr_t dev __unused, uint64_t addr) +{ + return addr; +} + #endif -- 2.7.4