From mboxrd@z Thu Jan 1 00:00:00 1970 From: Liran Alon Subject: [PATCH v2 2/5] KVM: nVMX: Re-evaluate L1 pending events when running L2 and L1 got posted-interrupt Date: Tue, 5 Dec 2017 10:16:23 +0200 Message-ID: <1512461786-6465-3-git-send-email-liran.alon@oracle.com> References: <1512461786-6465-1-git-send-email-liran.alon@oracle.com> Cc: jmattson@google.com, wanpeng.li@hotmail.com, idan.brown@oracle.com, Liran Alon , Krish Sadhukhan , Konrad Rzeszutek Wilk To: pbonzini@redhat.com, rkrcmar@redhat.com, kvm@vger.kernel.org Return-path: Received: from userp1040.oracle.com ([156.151.31.81]:25262 "EHLO userp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752042AbdLEIRH (ORCPT ); Tue, 5 Dec 2017 03:17:07 -0500 In-Reply-To: <1512461786-6465-1-git-send-email-liran.alon@oracle.com> Sender: kvm-owner@vger.kernel.org List-ID: In case posted-interrupt was delivered to CPU while it is in host (outside guest), then posted-interrupt delivery will be done by calling sync_pir_to_irr() at vmentry after interrupts are disabled. sync_pir_to_irr() will check if vmx->pi_desc.control ON bit and if set, it will sync vmx->pi_desc.pir to IRR and afterwards update RVI to ensure virtual-interrupt-delivery will dispatch interrupt to guest. However, it is possible that L1 will receive a posted-interrupt while CPU runs at host and is about to enter L2. In this case, the call to sync_pir_to_irr() will indeed update the L1's APIC IRR but vcpu_enter_guest() will then just resume into L2 guest without re-evaluating if it should exit from L2 to L1 as a result of this new pending L1 event. To address this case, if sync_pir_to_irr() has a new L1 injectable interrupt and CPU is running L2, we set KVM_REQ_EVENT. This will cause vcpu_enter_guest() to run another iteration of evaluating pending KVM requests and will therefore consume KVM_REQ_EVENT which will make sure to call check_nested_events() which will handle the pending L1 event properly. Signed-off-by: Liran Alon Reviewed-by: Nikita Leshenko Reviewed-by: Krish Sadhukhan Signed-off-by: Krish Sadhukhan Signed-off-by: Konrad Rzeszutek Wilk --- arch/x86/kvm/vmx.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index f5074ec5701b..47bbb8b691e8 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -9031,20 +9031,33 @@ static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx = to_vmx(vcpu); + int prev_max_irr; int max_irr; WARN_ON(!vcpu->arch.apicv_active); + + prev_max_irr = kvm_lapic_find_highest_irr(vcpu); if (pi_test_on(&vmx->pi_desc)) { pi_clear_on(&vmx->pi_desc); + /* * IOMMU can write to PIR.ON, so the barrier matters even on UP. * But on x86 this is just a compiler barrier anyway. */ smp_mb__after_atomic(); max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir); + + /* + * If we are running L2 and L1 has a new pending interrupt + * which can be injected, we should re-evaluate + * what should be done with this new L1 interrupt. + */ + if (is_guest_mode(vcpu) && (max_irr > prev_max_irr)) + kvm_make_request(KVM_REQ_EVENT, vcpu); } else { - max_irr = kvm_lapic_find_highest_irr(vcpu); + max_irr = prev_max_irr; } + vmx_hwapic_irr_update(vcpu, max_irr); return max_irr; } -- 1.9.1