From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Woodhouse Subject: Re: [RFC 05/10] x86/speculation: Add basic IBRS support infrastructure Date: Wed, 24 Jan 2018 09:02:21 +0000 Message-ID: <1516784541.13558.90.camel@infradead.org> References: <1516476182-5153-1-git-send-email-karahmed@amazon.de> <1516476182-5153-6-git-send-email-karahmed@amazon.de> <1516741116.13558.11.camel@infradead.org> <20180124084735.GM2228@hirez.programming.kicks-ass.net> Mime-Version: 1.0 Content-Type: multipart/signed; micalg="sha-256"; protocol="application/x-pkcs7-signature"; boundary="=-oGndH9L9+zjA+3If/9ts" Cc: Thomas Gleixner , KarimAllah Ahmed , linux-kernel@vger.kernel.org, Andi Kleen , Andrea Arcangeli , Andy Lutomirski , Arjan van de Ven , Ashok Raj , Asit Mallick , Borislav Petkov , Dan Williams , Dave Hansen , Greg Kroah-Hartman , "H . Peter Anvin" , Ingo Molnar , Janakarajan Natarajan , Joerg Roedel , Jun Nakajima , Laura Abbott , Linus Torvalds Return-path: In-Reply-To: <20180124084735.GM2228@hirez.programming.kicks-ass.net> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org --=-oGndH9L9+zjA+3If/9ts Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2018-01-24 at 09:47 +0100, Peter Zijlstra wrote: > Typically tglx likes to use x86_match_cpu() for these things; see also > commit: bd9240a18edfb ("x86/apic: Add TSC_DEADLINE quirk due to > errata"). Thanks, will fix. I think we might also end up in whitelist mode, adding "known good" microcodes to the list as they get released or retroactively blessed. I would really have liked a new bit in IA32_ARCH_CAPABILITIES to say that it's safe, but that's not possible for *existing* microcode which actually turns out to be OK in the end. That means the whitelist ends up basically empty right now. Should I add a command line parameter to override it? Otherwise we end up having to rebuild the kernel every time there's a microcode release which covers a new CPU SKU (which is why I kind of hate the whitelist, but Arjan is very insistent...) I'm kind of tempted to turn it into a whitelist just by adding 1 to the microcode revision in each table entry. Sure, that N+1 might be another microcode build that also has issues but never saw the light of day... but that's OK as long it never *does*. And yes we'd have to tweak it if revisions that are blacklisted in the Intel doc are subsequently cleared. But at least it'd require *less* tweaking. > >=20 > > + > > +static int bad_spectre_microcode(struct cpuinfo_x86 *c) > > +{ > > + int i; > > + > > + for (i =3D 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { > > + if (c->x86_model =3D=3D spectre_bad_microcodes[i].model && > > + =C2=A0=C2=A0=C2=A0=C2=A0c->x86_mask =3D=3D spectre_bad_microcodes[i]= .stepping) > > + return (c->microcode <=3D spectre_bad_microcodes[i].microcode); > > + } > > + return 0; > > +} > The above is Intel only, you should check vendor too I think. It's in intel.c, called from early_init_intel(). Isn't that sufficient? > >=20 > > =C2=A0static void early_init_intel(struct cpuinfo_x86 *c) > > =C2=A0{ > > =C2=A0 u64 misc_enable; > > @@ -122,6 +173,18 @@ static void early_init_intel(struct cpuinfo_x86 *c= ) > > =C2=A0 if (c->x86 >=3D 6 && !cpu_has(c, X86_FEATURE_IA64)) > > =C2=A0 c->microcode =3D intel_get_microcode_revision(); > > =C2=A0 > > + if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0cpu_has(c, X86_FEATURE_AMD_SPEC_CTRL) |= | > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0cpu_has(c, X86_FEATURE_AMD_PRED_CMD) || > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0cpu_has(c, X86_FEATURE_AMD_STIBP)) && b= ad_spectre_microcode(c)) { > > + pr_warn("Intel Spectre v2 broken microcode detected; disabling SPEC_= CTRL\n"); > > + clear_cpu_cap(c, X86_FEATURE_SPEC_CTRL); > > + clear_cpu_cap(c, X86_FEATURE_STIBP); > > + clear_cpu_cap(c, X86_FEATURE_AMD_SPEC_CTRL); > > + clear_cpu_cap(c, X86_FEATURE_AMD_PRED_CMD); > > + clear_cpu_cap(c, X86_FEATURE_AMD_STIBP); > > + } > And since its Intel only, what are those AMD features doing there? Hypervisors which only want to expose PRED_CMD may do so using the AMD feature bit. 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