From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Woodhouse Subject: Re: [RFC 09/10] x86/enter: Create macros to restrict/unrestrict Indirect Branch Speculation Date: Fri, 26 Jan 2018 17:31:45 +0000 Message-ID: <1516987905.30244.250.camel@infradead.org> References: <7c0b0879-3448-43e4-8380-4708fc787113@default> <50c5d627-8975-184b-b50f-4cc02c5816c5@intel.com> <1516957886.30244.161.camel@infradead.org> <1516987778.30244.247.camel@infradead.org> Mime-Version: 1.0 Content-Type: multipart/signed; micalg="sha-256"; protocol="application/x-pkcs7-signature"; boundary="=-ygWJUuRWoq1iHv89oqBL" Cc: Dave Hansen , Liran Alon , Laura Abbott , Andrew Lutomirski , Janakarajan Natarajan , Borislav Petkov , "Mallick, Asit K" , Radim =?UTF-8?Q?Kr=C4=8Dm=C3=A1=C5=99?= , KarimAllah Ahmed , Peter Anvin , Jun Nakajima , Ingo Molnar , the arch/x86 maintainers , Ashok Raj , "Van De Ven, Arjan" , Tim Chen , Paolo Bonzini , Andi Kleen , Linux Kernel Mailing List Return-path: In-Reply-To: <1516987778.30244.247.camel@infradead.org> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org --=-ygWJUuRWoq1iHv89oqBL Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2018-01-26 at 17:29 +0000, David Woodhouse wrote: > On Fri, 2018-01-26 at 09:19 -0800, Linus Torvalds wrote: > > On Fri, Jan 26, 2018 at 1:11 AM, David Woodhouse = wrote: > > > Do we need to look again at the fact that we've disabled the RSB- > > > stuffing for SMEP? > > > > Absolutely. SMEP helps make people a lot less worried about things, > > but it doesn't fix the "BTB only contains partial addresses" case. > >=20 > > But did we do that "disable stuffing with SMEP"? I'm not seeing it. In > > my tree, it's only conditional on X86_FEATURE_RETPOLINE. > > That's the vmexit one. The one on context switch is in > commit=C2=A0c995efd5a7 and has its own X86_FEATURE_RSB_CTXSW which in > kernel/cpu/bugs.c is turned on for (!SMEP || Skylake). >=20 > The "low bits of the BTB" issue probably means that wants to be > X86_FEATURE_RETPOLINE too. Despite Intel's doc saying otherwise. >=20 > (Intel's doc also says to do it on kernel entry, but we elected to do > it on context switch instead since *that's* when the imbalances show up > in the RSB.) Note, we've switched from talking about BTB to RSB here, so this is a valid concern if the *RSB* only has the low bits of the target. --=-ygWJUuRWoq1iHv89oqBL Content-Type: application/x-pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExDzANBglghkgBZQMEAgEFADCABgkqhkiG9w0BBwEAAKCCEFQw ggUxMIIEGaADAgECAhBNRhEyk/HZ7naOeTHWrzuAMA0GCSqGSIb3DQEBCwUAMIGXMQswCQYDVQQG EwJHQjEbMBkGA1UECBMSR3JlYXRlciBNYW5jaGVzdGVyMRAwDgYDVQQHEwdTYWxmb3JkMRowGAYD VQQKExFDT01PRE8gQ0EgTGltaXRlZDE9MDsGA1UEAxM0Q09NT0RPIFJTQSBDbGllbnQgQXV0aGVu dGljYXRpb24gYW5kIFNlY3VyZSBFbWFpbCBDQTAeFw0xNzEyMjEwMDAwMDBaFw0xODEyMjEyMzU5 NTlaMCQxIjAgBgkqhkiG9w0BCQEWE2R3bXcyQGluZnJhZGVhZC5vcmcwggEiMA0GCSqGSIb3DQEB AQUAA4IBDwAwggEKAoIBAQDgzLNWa18DNpGUj/ZeH0Sgz53ESIbzdPw3OJeuNP6jZhxZojbyfxbM hETscxI/Hj6UZ4a7sHm5BkVjlsB1Af2Za/PXUt8MmLAcPMHkMPGunvkUibEvblDvpqMkQZlaZM+t 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