From: Fenghua Yu <fenghua.yu@intel.com>
To: "Thomas Gleixner" <tglx@linutronix.de>,
"Ingo Molnar" <mingo@redhat.com>,
"Borislav Petkov" <bp@alien8.de>, "H Peter Anvin" <hpa@zytor.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Dave Hansen" <dave.hansen@intel.com>,
"Ashok Raj" <ashok.raj@intel.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Ravi V Shankar" <ravi.v.shankar@intel.com>,
"Xiaoyao Li " <xiaoyao.li@intel.com>
Cc: "linux-kernel" <linux-kernel@vger.kernel.org>,
"x86" <x86@kernel.org>,
kvm@vger.kernel.org, Fenghua Yu <fenghua.yu@intel.com>
Subject: [PATCH v4 05/17] x86/cpufeatures: Enumerate IA32_CORE_CAPABILITIES MSR
Date: Fri, 1 Mar 2019 18:44:59 -0800 [thread overview]
Message-ID: <1551494711-213533-6-git-send-email-fenghua.yu@intel.com> (raw)
In-Reply-To: <1551494711-213533-1-git-send-email-fenghua.yu@intel.com>
MSR register IA32_CORE_CAPABILITIES (0xCF) contains bits that enumerate
some model specific features.
The MSR 0xCF itself is enumerated by CPUID.(EAX=0x7,ECX=0):EDX[30].
When this bit is 1, the MSR 0xCF exists.
Detailed information for the CPUID bit and the MSR can be found in the
latest Intel Architecture Instruction Set Extensions and Future Features
Programming Reference.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 6d6122524711..350eeccd0ce9 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -349,6 +349,7 @@
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
+#define X86_FEATURE_CORE_CAPABILITY (18*32+30) /* IA32_CORE_CAPABILITY MSR */
#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
/*
--
2.7.4
next prev parent reply other threads:[~2019-03-02 2:44 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-02 2:44 [PATCH v4 00/17] x86/split_lock: Enable #AC exception for split locked accesses Fenghua Yu
2019-03-02 2:44 ` [PATCH v4 01/17] x86/common: Align cpu_caps_cleared and cpu_caps_set to unsigned long Fenghua Yu
2019-03-04 8:33 ` Paolo Bonzini
2019-03-04 10:17 ` Peter Zijlstra
2019-03-04 10:48 ` Paolo Bonzini
2019-03-04 12:44 ` Peter Zijlstra
2019-03-04 13:13 ` Paolo Bonzini
2019-03-02 2:44 ` [PATCH v4 02/17] drivers/net/b44: Align pwol_mask to unsigned long for better performance Fenghua Yu
2019-03-04 10:00 ` Peter Zijlstra
2019-03-04 14:45 ` Fenghua Yu
2019-03-04 15:27 ` Peter Zijlstra
2019-03-02 2:44 ` [PATCH v4 03/17] wlcore: Align reg_ch_conf_pending and tmp_ch_bitmap " Fenghua Yu
2019-03-04 10:11 ` Peter Zijlstra
2019-03-04 10:46 ` Paolo Bonzini
2019-03-04 12:41 ` Peter Zijlstra
2019-03-04 13:09 ` Paolo Bonzini
2019-03-04 13:30 ` Peter Zijlstra
2019-03-04 14:40 ` Fenghua Yu
2019-03-04 15:54 ` Paolo Bonzini
2019-03-02 2:44 ` [PATCH v4 04/17] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access Fenghua Yu
2019-03-04 18:52 ` Dave Hansen
2019-03-04 19:15 ` Fenghua Yu
2019-03-04 19:29 ` Dave Hansen
2019-03-04 20:08 ` Peter Zijlstra
2019-03-04 20:12 ` Peter Zijlstra
2019-03-02 2:44 ` Fenghua Yu [this message]
2019-03-04 18:53 ` [PATCH v4 05/17] x86/cpufeatures: Enumerate IA32_CORE_CAPABILITIES MSR Dave Hansen
2019-03-04 18:55 ` Yu, Fenghua
2019-03-04 19:01 ` Dave Hansen
2019-03-02 2:45 ` [PATCH v4 06/17] x86/msr-index: Define IA32_CORE_CAPABILITY MSR and #AC exception for split lock bit Fenghua Yu
2019-03-02 2:45 ` [PATCH v4 07/17] x86/split_lock: Enumerate #AC for split lock by MSR IA32_CORE_CAPABILITY Fenghua Yu
2019-03-04 18:58 ` Dave Hansen
2019-03-04 18:59 ` Fenghua Yu
2019-03-04 19:19 ` Dave Hansen
2019-03-02 2:45 ` [PATCH v4 08/17] x86/clearcpuid: Support multiple clearcpuid options Fenghua Yu
2019-03-02 2:45 ` [PATCH v4 09/17] x86/clearcpuid: Support feature flag string in kernel option clearcpuid Fenghua Yu
2019-03-02 2:45 ` [PATCH v4 10/17] x86/clearcpuid: Apply cleared feature bits that are forced set before Fenghua Yu
2019-03-02 2:45 ` [PATCH v4 11/17] x86/clearcpuid: Clear CPUID bit in CPUID faulting Fenghua Yu
2019-03-04 22:04 ` kbuild test robot
2019-03-05 7:27 ` kbuild test robot
2019-03-02 2:45 ` [PATCH v4 12/17] Change document for kernel option clearcpuid Fenghua Yu
2019-03-02 2:45 ` [PATCH v4 13/17] x86/split_lock: Handle #AC exception for split lock Fenghua Yu
2019-03-02 2:45 ` [PATCH v4 14/17] x86/split_lock: Add a sysfs interface to allow user to enable or disable split lock detection on all CPUs during run time Fenghua Yu
2019-03-02 2:45 ` [PATCH v4 15/17] kvm: x86: Report CORE_CAPABILITY on GET_SUPPORTED_CPUID Fenghua Yu
2019-03-04 8:38 ` Paolo Bonzini
2019-03-04 10:47 ` Xiaoyao Li
2019-03-04 10:49 ` Paolo Bonzini
2019-03-04 11:10 ` Xiaoyao Li
2019-03-04 11:14 ` Paolo Bonzini
2019-03-04 11:21 ` Xiaoyao Li
2019-03-05 7:03 ` Xiaoyao Li
2019-03-02 2:45 ` [PATCH v4 16/17] kvm: x86: Add support IA32_CORE_CAPABILITY MSR Fenghua Yu
2019-03-04 8:42 ` Paolo Bonzini
2019-03-04 12:32 ` Xiaoyao Li
2019-03-08 6:10 ` Xiaoyao Li
2019-03-08 7:54 ` Paolo Bonzini
2019-03-08 8:03 ` Xiaoyao Li
2019-03-02 2:45 ` [PATCH v4 17/17] kvm: vmx: Emulate TEST_CTL MSR Fenghua Yu
2019-03-09 2:31 ` Xiaoyao Li
2019-03-11 13:31 ` Paolo Bonzini
2019-03-11 15:10 ` Xiaoyao Li
2019-03-11 15:21 ` Paolo Bonzini
2019-03-11 16:58 ` Xiaoyao Li
2019-03-04 21:55 ` [PATCH v4 00/17] x86/split_lock: Enable #AC exception for split locked accesses Konrad Rzeszutek Wilk
2019-03-05 0:06 ` Fenghua Yu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1551494711-213533-6-git-send-email-fenghua.yu@intel.com \
--to=fenghua.yu@intel.com \
--cc=ashok.raj@intel.com \
--cc=bp@alien8.de \
--cc=dave.hansen@intel.com \
--cc=hpa@zytor.com \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=pbonzini@redhat.com \
--cc=peterz@infradead.org \
--cc=ravi.v.shankar@intel.com \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
--cc=xiaoyao.li@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox