From mboxrd@z Thu Jan 1 00:00:00 1970 From: Fenghua Yu Subject: [PATCH v4 06/17] x86/msr-index: Define IA32_CORE_CAPABILITY MSR and #AC exception for split lock bit Date: Fri, 1 Mar 2019 18:45:00 -0800 Message-ID: <1551494711-213533-7-git-send-email-fenghua.yu@intel.com> References: <1551494711-213533-1-git-send-email-fenghua.yu@intel.com> Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " Return-path: In-Reply-To: <1551494711-213533-1-git-send-email-fenghua.yu@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org A new IA32_CORE_CAPABILITY MSR (0xCF) is defined. Each bit in the MSR enumerates a model specific feature. Currently bit 5 enumerates #AC exception for split locked accesses. When bit 5 is 1, split locked accesses will generate #AC exception. When bit 5 is 0, split locked accesses will not generate #AC exception. Please check the latest Intel Architecture Instruction Set Extensions and Future Features Programming Reference for more detailed information on the MSR and the split lock bit. Signed-off-by: Fenghua Yu --- arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 8e40c2446fd1..549e73dcca15 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -59,6 +59,9 @@ #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) +#define MSR_IA32_CORE_CAPABILITY 0x000000cf +#define CORE_CAP_SPLIT_LOCK_DETECT BIT(5) /* Detect split lock */ + #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26) -- 2.7.4