From mboxrd@z Thu Jan 1 00:00:00 1970 From: Fenghua Yu Subject: [PATCH v6 06/20] x86/cpufeatures: Enumerate MSR_IA32_CORE_CAPABILITY Date: Wed, 3 Apr 2019 14:21:52 -0700 Message-ID: <1554326526-172295-7-git-send-email-fenghua.yu@intel.com> References: <1554326526-172295-1-git-send-email-fenghua.yu@intel.com> Cc: "linux-kernel" , "x86" , linux-wireless@vger.kernel.org, netdev@vger.kernel.org, kvm@vger.kernel.org, Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Dave Hansen" , "Paolo Bonzini" , "Ashok Raj" , "Peter Zijlstra" , "Kalle Valo" , "Xiaoyao Li " , "Michael Chan" , "Ravi V Shankar" Return-path: In-Reply-To: <1554326526-172295-1-git-send-email-fenghua.yu@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org MSR_IA32_CORE_CAPABILITY (0xcf) contains bits that enumerate some model specific features. The MSR 0xcf itself is enumerated by CPUID.(EAX=0x7,ECX=0):EDX[30]. When this CPUID bit is 1, the MSR 0xcf exists. Detailed information on the CPUID bit and the MSR can be found in the latest Intel 64 and IA-32 Architectures Software Developer's Manual. Signed-off-by: Fenghua Yu --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 981ff9479648..eff25e2015a5 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -350,6 +350,7 @@ #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */ #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ +#define X86_FEATURE_CORE_CAPABILITY (18*32+30) /* "" IA32_CORE_CAPABILITY MSR */ #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */ /* -- 2.19.1