From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1ED1C43219 for ; Fri, 26 Apr 2019 03:19:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D01F620675 for ; Fri, 26 Apr 2019 03:19:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728179AbfDZDTO (ORCPT ); Thu, 25 Apr 2019 23:19:14 -0400 Received: from mga02.intel.com ([134.134.136.20]:27433 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726855AbfDZDTO (ORCPT ); Thu, 25 Apr 2019 23:19:14 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Apr 2019 20:19:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,396,1549958400"; d="scan'208";a="319087374" Received: from xulike-server.sh.intel.com ([10.239.48.134]) by orsmga005.jf.intel.com with ESMTP; 25 Apr 2019 20:19:12 -0700 From: Like Xu To: kvm@vger.kernel.org Cc: Sean Christopherson , Xiaoyao Li , Paolo Bonzini , Konrad Rzeszutek Wilk , linux-kernel@vger.kernel.org Subject: [PATCH v2] KVM: x86: Add Intel CPUID.1F cpuid emulation support Date: Fri, 26 Apr 2019 11:17:52 +0800 Message-Id: <1556248672-6469-1-git-send-email-like.xu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Some new systems have multiple software-visible die within each package. Add support to expose Intel V2 Extended Topology Enumeration Leaf CPUID.1F. Co-developed-by: Xiaoyao Li Signed-off-by: Xiaoyao Li Signed-off-by: Like Xu --- ==changelog== v2: - Apply cpuid.1f check rule on Intel SDM page 3-222 Vol.2A - Add comment to handle 0x1f anf 0xb in common code - Reduce check time in a descending-break style v1: https://lkml.org/lkml/2019/4/22/28 arch/x86/kvm/cpuid.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index fd39516..f9b529e 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -425,6 +425,11 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, switch (function) { case 0: + /* Check if the cpuid leaf 0x1f is actually implemented */ + if (entry->eax >= 0x1f && (cpuid_ebx(0x1f) & 0x0000ffff)) { + entry->eax = 0x1f; + break; + } entry->eax = min(entry->eax, (u32)(f_intel_pt ? 0x14 : 0xd)); break; case 1: @@ -544,7 +549,12 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, entry->edx = edx.full; break; } - /* function 0xb has additional index. */ + /* + * Intel documentation states that 0x1f and 0xb have + * identical formats and thus can be handled by common code. + * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) + */ + case 0x1f: case 0xb: { int i, level_type; -- 1.8.3.1