[PATCH v8 0/5] Add Svade and Svadu Extensions Support

[PATCH v8 0/5] Add Svade and Svadu Extensions Support

[Yong-Xuan Wang]

Svade and Svadu extensions represent two schemes for managing the PTE A/D
bit. When the PTE A/D bits need to be set, Svade extension intdicates that
a related page fault will be raised. In contrast, the Svadu extension
supports hardware updating of PTE A/D bits. This series enables Svade and
Svadu extensions for both host and guest OS.

Regrading the mailing thread[1], we have 4 possible combinations of
these extensions in the device tree, the default hardware behavior for
these possibilities are:
1) Neither Svade nor Svadu present in DT => It is technically
   unknown whether the platform uses Svade or Svadu. Supervisor
   software should be prepared to handle either hardware updating
   of the PTE A/D bits or page faults when they need updated.
2) Only Svade present in DT => Supervisor must assume Svade to be
   always enabled.
3) Only Svadu present in DT => Supervisor must assume Svadu to be
   always enabled.
4) Both Svade and Svadu present in DT => Supervisor must assume
   Svadu turned-off at boot time. To use Svadu, supervisor must
   explicitly enable it using the SBI FWFT extension.

The Svade extension is mandatory and the Svadu extension is optional in
RVA23 profile. Platforms want to take the advantage of Svadu can choose
3. Those are aware of the profile can choose 4, and Linux won't get the
benefit of svadu until the SBI FWFT extension is available.

[1] https://lore.kernel.org/linux-kernel/20240527-e9845c06619bca5cd285098c@orel/T/#m29644eb88e241ec282df4ccd5199514e913b06ee

---
v8:
- fix typo in PATCH1 (Samuel)
- use the new extension validating API in PATCH1 (Clément)
- update the dtbinding in PATCH2 (Samuel, Conor)
- add PATCH4 to fix compile error in get-reg-list test.

v7:
- fix alignment in PATCH1
- update the dtbinding in PATCH2 (Conor, Jessica)

v6:
- reflect the platform's behavior by riscv_isa_extension_available() and
  update the the arch_has_hw_pte_young() in PATCH1 (Conor, Andrew)
- update the dtbinding in PATCH2 (Alexandre, Andrew, Anup, Conor)
- update the henvcfg condition in PATCH3 (Andrew)
- check if Svade is allowed to disabled based on arch_has_hw_pte_young()
  in PATCH3

v5:
- remove all Acked-by and Reviewed-by (Conor, Andrew)
- add Svade support
- update the arch_has_hw_pte_young() in PATCH1
- update the dtbinding in PATCH2 (Alexandre, Andrew)
- check the availibility of Svadu for Guest/VM based on
  arch_has_hw_pte_young() in PATCH3

v4:
- fix 32bit kernel build error in PATCH1 (Conor)
- update the status of Svadu extension to ratified in PATCH2
- add the PATCH4 to suporrt SBI_FWFT_PTE_AD_HW_UPDATING for guest OS
- update the PATCH1 and PATCH3 to integrate with FWFT extension
- rebase PATCH5 on the lastest get-reg-list test (Andrew)

v3:
- fix the control bit name to ADUE in PATCH1 and PATCH3
- update get-reg-list in PATCH4

v2:
- add Co-developed-by: in PATCH1
- use riscv_has_extension_unlikely() to runtime patch the branch in PATCH1
- update dt-binding

Yong-Xuan Wang (5):
  RISC-V: Add Svade and Svadu Extensions Support
  dt-bindings: riscv: Add Svade and Svadu Entries
  RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM
  KVM: riscv: selftests: Fix compile error
  KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list
    test

 .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++
 arch/riscv/Kconfig                            |  1 +
 arch/riscv/include/asm/csr.h                  |  1 +
 arch/riscv/include/asm/hwcap.h                |  2 ++
 arch/riscv/include/asm/pgtable.h              | 13 ++++++++-
 arch/riscv/include/uapi/asm/kvm.h             |  2 ++
 arch/riscv/kernel/cpufeature.c                | 12 ++++++++
 arch/riscv/kvm/vcpu.c                         |  4 +++
 arch/riscv/kvm/vcpu_onereg.c                  | 15 ++++++++++
 .../selftests/kvm/riscv/get-reg-list.c        | 16 ++++++++---
 10 files changed, 89 insertions(+), 5 deletions(-)

-- 
2.17.1

[PATCH v8 1/5] RISC-V: Add Svade and Svadu Extensions Support

[Yong-Xuan Wang]

Svade and Svadu extensions represent two schemes for managing the PTE A/D
bits. When the PTE A/D bits need to be set, Svade extension intdicates
that a related page fault will be raised. In contrast, the Svadu extension
supports hardware updating of PTE A/D bits. Since the Svade extension is
mandatory and the Svadu extension is optional in RVA23 profile, by default
the M-mode firmware will enable the Svadu extension in the menvcfg CSR
when only Svadu is present in DT.

This patch detects Svade and Svadu extensions from DT and adds
arch_has_hw_pte_young() to enable optimization in MGLRU and
__wp_page_copy_user() when we have the PTE A/D bits hardware updating
support.

Co-developed-by: Jinyu Tang <tjytimi@163.com>
Signed-off-by: Jinyu Tang <tjytimi@163.com>
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
---
 arch/riscv/Kconfig               |  1 +
 arch/riscv/include/asm/csr.h     |  1 +
 arch/riscv/include/asm/hwcap.h   |  2 ++
 arch/riscv/include/asm/pgtable.h | 13 ++++++++++++-
 arch/riscv/kernel/cpufeature.c   | 12 ++++++++++++
 5 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3ceec2ca84fa..014e512854a6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -29,6 +29,7 @@ config RISCV
 	select ARCH_HAS_FORTIFY_SOURCE
 	select ARCH_HAS_GCOV_PROFILE_ALL
 	select ARCH_HAS_GIGANTIC_PAGE
+	select ARCH_HAS_HW_PTE_YOUNG
 	select ARCH_HAS_KCOV
 	select ARCH_HAS_KERNEL_FPU_SUPPORT if 64BIT && FPU
 	select ARCH_HAS_MEMBARRIER_CALLBACKS
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 25966995da04..524cd4131c71 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -195,6 +195,7 @@
 /* xENVCFG flags */
 #define ENVCFG_STCE			(_AC(1, ULL) << 63)
 #define ENVCFG_PBMTE			(_AC(1, ULL) << 62)
+#define ENVCFG_ADUE			(_AC(1, ULL) << 61)
 #define ENVCFG_CBZE			(_AC(1, UL) << 7)
 #define ENVCFG_CBCFE			(_AC(1, UL) << 6)
 #define ENVCFG_CBIE_SHIFT		4
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index b18b202ca141..b0435fda09ae 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -93,6 +93,8 @@
 #define RISCV_ISA_EXT_ZCF		84
 #define RISCV_ISA_EXT_ZCMOP		85
 #define RISCV_ISA_EXT_ZAWRS		86
+#define RISCV_ISA_EXT_SVADE		87
+#define RISCV_ISA_EXT_SVADU		88
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 089f3c9f56a3..6f1a0534f319 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -120,6 +120,7 @@
 #include <asm/tlbflush.h>
 #include <linux/mm_types.h>
 #include <asm/compat.h>
+#include <asm/cpufeature.h>
 
 #define __page_val_to_pfn(_val)  (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT)
 
@@ -288,7 +289,6 @@ static inline pte_t pud_pte(pud_t pud)
 }
 
 #ifdef CONFIG_RISCV_ISA_SVNAPOT
-#include <asm/cpufeature.h>
 
 static __always_inline bool has_svnapot(void)
 {
@@ -649,6 +649,17 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
 	return __pgprot(prot);
 }
 
+/*
+ * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
+ * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
+ * DT.
+ */
+#define arch_has_hw_pte_young arch_has_hw_pte_young
+static inline bool arch_has_hw_pte_young(void)
+{
+	return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);
+}
+
 /*
  * THP functions
  */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 0366dc3baf33..2a9cdfae21c6 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -156,6 +156,16 @@ static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data,
 	return -EPROBE_DEFER;
 }
 
+static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,
+				    const unsigned long *isa_bitmap)
+{
+	/* SVADE has already been detected, use SVADE only */
+	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SVADE))
+		return -EOPNOTSUPP;
+
+	return 0;
+}
+
 static const unsigned int riscv_zk_bundled_exts[] = {
 	RISCV_ISA_EXT_ZBKB,
 	RISCV_ISA_EXT_ZBKC,
@@ -402,6 +412,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
+	__RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
+	__RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),
 	__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
 	__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
 	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
-- 
2.17.1

[PATCH v8 2/5] dt-bindings: riscv: Add Svade and Svadu Entries

[Yong-Xuan Wang]

Add entries for the Svade and Svadu extensions to the riscv,isa-extensions
property.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
---
 .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index a06dbc6b4928..b3885756766d 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -153,6 +153,34 @@ properties:
             ratified at commit 3f9ed34 ("Add ability to manually trigger
             workflow. (#2)") of riscv-time-compare.
 
+        - const: svade
+          description: |
+            The standard Svade supervisor-level extension for SW-managed PTE A/D
+            bit updates as ratified in the 20240213 version of the privileged
+            ISA specification.
+
+            Both Svade and Svadu extensions control the hardware behavior when
+            the PTE A/D bits need to be set. The default behavior for the four
+            possible combinations of these extensions in the device tree are:
+            1) Neither Svade nor Svadu present in DT => It is technically
+               unknown whether the platform uses Svade or Svadu. Supervisor
+               software should be prepared to handle either hardware updating
+               of the PTE A/D bits or page faults when they need updated.
+            2) Only Svade present in DT => Supervisor must assume Svade to be
+               always enabled.
+            3) Only Svadu present in DT => Supervisor must assume Svadu to be
+               always enabled.
+            4) Both Svade and Svadu present in DT => Supervisor must assume
+               Svadu turned-off at boot time. To use Svadu, supervisor must
+               explicitly enable it using the SBI FWFT extension.
+
+        - const: svadu
+          description: |
+            The standard Svadu supervisor-level extension for hardware updating
+            of PTE A/D bits as ratified in the 20240528 version of the
+            privileged ISA specification. Please refer to Svade dt-binding
+            description for more details.
+
         - const: svinval
           description:
             The standard Svinval supervisor-level extension for fine-grained
-- 
2.17.1

[PATCH v8 3/5] RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM

[Yong-Xuan Wang]

We extend the KVM ISA extension ONE_REG interface to allow VMM tools to
detect and enable Svade and Svadu extensions for Guest/VM. Since the
henvcfg.ADUE is read-only zero if the menvcfg.ADUE is zero, the Svadu
extension is available for Guest/VM and the Svade extension is allowed
to disabledonly when arch_has_hw_pte_young() is true.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
---
 arch/riscv/include/uapi/asm/kvm.h |  2 ++
 arch/riscv/kvm/vcpu.c             |  4 ++++
 arch/riscv/kvm/vcpu_onereg.c      | 15 +++++++++++++++
 3 files changed, 21 insertions(+)

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index e97db3296456..85bbc472989d 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -175,6 +175,8 @@ enum KVM_RISCV_ISA_EXT_ID {
 	KVM_RISCV_ISA_EXT_ZCF,
 	KVM_RISCV_ISA_EXT_ZCMOP,
 	KVM_RISCV_ISA_EXT_ZAWRS,
+	KVM_RISCV_ISA_EXT_SVADE,
+	KVM_RISCV_ISA_EXT_SVADU,
 	KVM_RISCV_ISA_EXT_MAX,
 };
 
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 8d7d381737ee..c78061a6d68b 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -544,6 +544,10 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu)
 	if (riscv_isa_extension_available(isa, ZICBOZ))
 		cfg->henvcfg |= ENVCFG_CBZE;
 
+	if (riscv_isa_extension_available(isa, SVADU) &&
+	    !riscv_isa_extension_available(isa, SVADE))
+		cfg->henvcfg |= ENVCFG_ADUE;
+
 	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
 		cfg->hstateen0 |= SMSTATEEN0_HSENVCFG;
 		if (riscv_isa_extension_available(isa, SSAIA))
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index b319c4c13c54..b3f58908902a 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -15,6 +15,7 @@
 #include <asm/cacheflush.h>
 #include <asm/cpufeature.h>
 #include <asm/kvm_vcpu_vector.h>
+#include <asm/pgtable.h>
 #include <asm/vector.h>
 
 #define KVM_RISCV_BASE_ISA_MASK		GENMASK(25, 0)
@@ -38,6 +39,8 @@ static const unsigned long kvm_isa_ext_arr[] = {
 	KVM_ISA_EXT_ARR(SSAIA),
 	KVM_ISA_EXT_ARR(SSCOFPMF),
 	KVM_ISA_EXT_ARR(SSTC),
+	KVM_ISA_EXT_ARR(SVADE),
+	KVM_ISA_EXT_ARR(SVADU),
 	KVM_ISA_EXT_ARR(SVINVAL),
 	KVM_ISA_EXT_ARR(SVNAPOT),
 	KVM_ISA_EXT_ARR(SVPBMT),
@@ -110,6 +113,12 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext)
 	case KVM_RISCV_ISA_EXT_SSCOFPMF:
 		/* Sscofpmf depends on interrupt filtering defined in ssaia */
 		return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA);
+	case KVM_RISCV_ISA_EXT_SVADU:
+		/*
+		 * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.
+		 * Guest OS can use Svadu only when host OS enable Svadu.
+		 */
+		return arch_has_hw_pte_young();
 	case KVM_RISCV_ISA_EXT_V:
 		return riscv_v_vstate_ctrl_user_allowed();
 	default:
@@ -181,6 +190,12 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
 	/* Extensions which can be disabled using Smstateen */
 	case KVM_RISCV_ISA_EXT_SSAIA:
 		return riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN);
+	case KVM_RISCV_ISA_EXT_SVADE:
+		/*
+		 * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.
+		 * Svade is not allowed to disable when the platform use Svade.
+		 */
+		return arch_has_hw_pte_young();
 	default:
 		break;
 	}
-- 
2.17.1

[PATCH v8 4/5] KVM: riscv: selftests: Fix compile error

[Yong-Xuan Wang]

Fix compile error introduced by commit d27c34a73514 ("KVM: riscv:
selftests: Add some Zc* extensions to get-reg-list test"). These
4 lines should be end with ";".

Fixes: d27c34a73514 ("KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test")
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
---
 tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index f92c2fb23fcd..8e34f7fa44e9 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -961,10 +961,10 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB);
 KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC);
 KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX);
 KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS);
-KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA),
-KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB),
-KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD),
-KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF),
+KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA);
+KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB);
+KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD);
+KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF);
 KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP);
 KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
 KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
-- 
2.17.1

Re: [PATCH v8 4/5] KVM: riscv: selftests: Fix compile error

[Clément Léger]

On 26/07/2024 10:49, Yong-Xuan Wang wrote:
> Fix compile error introduced by commit d27c34a73514 ("KVM: riscv:
> selftests: Add some Zc* extensions to get-reg-list test"). These
> 4 lines should be end with ";".
> 
> Fixes: d27c34a73514 ("KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test")
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
>  tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index f92c2fb23fcd..8e34f7fa44e9 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -961,10 +961,10 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB);
>  KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC);
>  KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX);
>  KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS);
> -KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA),
> -KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB),
> -KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD),
> -KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF),
> +KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF);
>  KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP);
>  KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
>  KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);

Arg, my bad. Thanks for fixing that.

Reviewed-by: Clément Léger <cleger@rivosinc.com>

Thanks,

Clément

Re: [PATCH v8 4/5] KVM: riscv: selftests: Fix compile error

[Anup Patel]

On Fri, Jul 26, 2024 at 2:19 PM Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote:
>
> Fix compile error introduced by commit d27c34a73514 ("KVM: riscv:
> selftests: Add some Zc* extensions to get-reg-list test"). These
> 4 lines should be end with ";".
>
> Fixes: d27c34a73514 ("KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test")
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>

Queued this patch for Linux-6.11-rc1 fixes.

Thanks,
Anup

> ---
>  tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index f92c2fb23fcd..8e34f7fa44e9 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -961,10 +961,10 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB);
>  KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC);
>  KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX);
>  KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS);
> -KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA),
> -KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB),
> -KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD),
> -KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF),
> +KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF);
>  KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP);
>  KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
>  KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
> --
> 2.17.1
>

[PATCH v8 5/5] KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test

[Yong-Xuan Wang]

Update the get-reg-list test to test the Svade and Svadu Extensions are
available for guest OS.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index 8e34f7fa44e9..aac40652e181 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -45,6 +45,8 @@ bool filter_reg(__u64 reg)
 	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA:
 	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSCOFPMF:
 	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC:
+	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADE:
+	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADU:
 	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL:
 	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT:
 	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT:
@@ -418,6 +420,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
 		KVM_ISA_EXT_ARR(SSAIA),
 		KVM_ISA_EXT_ARR(SSCOFPMF),
 		KVM_ISA_EXT_ARR(SSTC),
+		KVM_ISA_EXT_ARR(SVADE),
+		KVM_ISA_EXT_ARR(SVADU),
 		KVM_ISA_EXT_ARR(SVINVAL),
 		KVM_ISA_EXT_ARR(SVNAPOT),
 		KVM_ISA_EXT_ARR(SVPBMT),
@@ -949,6 +953,8 @@ KVM_ISA_EXT_SIMPLE_CONFIG(h, H);
 KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN);
 KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF);
 KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC);
+KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE);
+KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU);
 KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);
 KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);
 KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);
@@ -1012,6 +1018,8 @@ struct vcpu_reg_list *vcpu_configs[] = {
 	&config_smstateen,
 	&config_sscofpmf,
 	&config_sstc,
+	&config_svade,
+	&config_svadu,
 	&config_svinval,
 	&config_svnapot,
 	&config_svpbmt,
-- 
2.17.1

Re: [PATCH v8 0/5] Add Svade and Svadu Extensions Support

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (fixes)
by Anup Patel <anup@brainfault.org>:

On Fri, 26 Jul 2024 16:49:25 +0800 you wrote:
> Svade and Svadu extensions represent two schemes for managing the PTE A/D
> bit. When the PTE A/D bits need to be set, Svade extension intdicates that
> a related page fault will be raised. In contrast, the Svadu extension
> supports hardware updating of PTE A/D bits. This series enables Svade and
> Svadu extensions for both host and guest OS.
> 
> Regrading the mailing thread[1], we have 4 possible combinations of
> these extensions in the device tree, the default hardware behavior for
> these possibilities are:
> 1) Neither Svade nor Svadu present in DT => It is technically
>    unknown whether the platform uses Svade or Svadu. Supervisor
>    software should be prepared to handle either hardware updating
>    of the PTE A/D bits or page faults when they need updated.
> 2) Only Svade present in DT => Supervisor must assume Svade to be
>    always enabled.
> 3) Only Svadu present in DT => Supervisor must assume Svadu to be
>    always enabled.
> 4) Both Svade and Svadu present in DT => Supervisor must assume
>    Svadu turned-off at boot time. To use Svadu, supervisor must
>    explicitly enable it using the SBI FWFT extension.
> 
> [...]

Here is the summary with links:
  - [v8,1/5] RISC-V: Add Svade and Svadu Extensions Support
    (no matching commit)
  - [v8,2/5] dt-bindings: riscv: Add Svade and Svadu Entries
    (no matching commit)
  - [v8,3/5] RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM
    (no matching commit)
  - [v8,4/5] KVM: riscv: selftests: Fix compile error
    https://git.kernel.org/riscv/c/dd4a799bcc13
  - [v8,5/5] KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test
    (no matching commit)

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html

Re: [PATCH v8 0/5] Add Svade and Svadu Extensions Support

[Anup Patel]

Hi Palmer,

On Fri, Jul 26, 2024 at 2:19 PM Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote:
>
> Svade and Svadu extensions represent two schemes for managing the PTE A/D
> bit. When the PTE A/D bits need to be set, Svade extension intdicates that
> a related page fault will be raised. In contrast, the Svadu extension
> supports hardware updating of PTE A/D bits. This series enables Svade and
> Svadu extensions for both host and guest OS.
>
> Regrading the mailing thread[1], we have 4 possible combinations of
> these extensions in the device tree, the default hardware behavior for
> these possibilities are:
> 1) Neither Svade nor Svadu present in DT => It is technically
>    unknown whether the platform uses Svade or Svadu. Supervisor
>    software should be prepared to handle either hardware updating
>    of the PTE A/D bits or page faults when they need updated.
> 2) Only Svade present in DT => Supervisor must assume Svade to be
>    always enabled.
> 3) Only Svadu present in DT => Supervisor must assume Svadu to be
>    always enabled.
> 4) Both Svade and Svadu present in DT => Supervisor must assume
>    Svadu turned-off at boot time. To use Svadu, supervisor must
>    explicitly enable it using the SBI FWFT extension.
>
> The Svade extension is mandatory and the Svadu extension is optional in
> RVA23 profile. Platforms want to take the advantage of Svadu can choose
> 3. Those are aware of the profile can choose 4, and Linux won't get the
> benefit of svadu until the SBI FWFT extension is available.
>
> [1] https://lore.kernel.org/linux-kernel/20240527-e9845c06619bca5cd285098c@orel/T/#m29644eb88e241ec282df4ccd5199514e913b06ee
>
> ---
> v8:
> - fix typo in PATCH1 (Samuel)
> - use the new extension validating API in PATCH1 (Clément)
> - update the dtbinding in PATCH2 (Samuel, Conor)
> - add PATCH4 to fix compile error in get-reg-list test.
>
> v7:
> - fix alignment in PATCH1
> - update the dtbinding in PATCH2 (Conor, Jessica)
>
> v6:
> - reflect the platform's behavior by riscv_isa_extension_available() and
>   update the the arch_has_hw_pte_young() in PATCH1 (Conor, Andrew)
> - update the dtbinding in PATCH2 (Alexandre, Andrew, Anup, Conor)
> - update the henvcfg condition in PATCH3 (Andrew)
> - check if Svade is allowed to disabled based on arch_has_hw_pte_young()
>   in PATCH3
>
> v5:
> - remove all Acked-by and Reviewed-by (Conor, Andrew)
> - add Svade support
> - update the arch_has_hw_pte_young() in PATCH1
> - update the dtbinding in PATCH2 (Alexandre, Andrew)
> - check the availibility of Svadu for Guest/VM based on
>   arch_has_hw_pte_young() in PATCH3
>
> v4:
> - fix 32bit kernel build error in PATCH1 (Conor)
> - update the status of Svadu extension to ratified in PATCH2
> - add the PATCH4 to suporrt SBI_FWFT_PTE_AD_HW_UPDATING for guest OS
> - update the PATCH1 and PATCH3 to integrate with FWFT extension
> - rebase PATCH5 on the lastest get-reg-list test (Andrew)
>
> v3:
> - fix the control bit name to ADUE in PATCH1 and PATCH3
> - update get-reg-list in PATCH4
>
> v2:
> - add Co-developed-by: in PATCH1
> - use riscv_has_extension_unlikely() to runtime patch the branch in PATCH1
> - update dt-binding
>
> Yong-Xuan Wang (5):
>   RISC-V: Add Svade and Svadu Extensions Support
>   dt-bindings: riscv: Add Svade and Svadu Entries
>   RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM
>   KVM: riscv: selftests: Fix compile error
>   KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list
>     test
>
>  .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++
>  arch/riscv/Kconfig                            |  1 +
>  arch/riscv/include/asm/csr.h                  |  1 +
>  arch/riscv/include/asm/hwcap.h                |  2 ++
>  arch/riscv/include/asm/pgtable.h              | 13 ++++++++-
>  arch/riscv/include/uapi/asm/kvm.h             |  2 ++
>  arch/riscv/kernel/cpufeature.c                | 12 ++++++++
>  arch/riscv/kvm/vcpu.c                         |  4 +++
>  arch/riscv/kvm/vcpu_onereg.c                  | 15 ++++++++++
>  .../selftests/kvm/riscv/get-reg-list.c        | 16 ++++++++---
>  10 files changed, 89 insertions(+), 5 deletions(-)
>
> --
> 2.17.1
>
>

Let me know if this series can be taken through the KVM RISC-V tree.
I can provide you with a shared tag as well.

Regards,
Anup

Re: [PATCH v8 0/5] Add Svade and Svadu Extensions Support

[Palmer Dabbelt]

On Wed, 21 Aug 2024 07:43:20 PDT (-0700), anup@brainfault.org wrote:
> Hi Palmer,
>
> On Fri, Jul 26, 2024 at 2:19 PM Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote:
>>
>> Svade and Svadu extensions represent two schemes for managing the PTE A/D
>> bit. When the PTE A/D bits need to be set, Svade extension intdicates that
>> a related page fault will be raised. In contrast, the Svadu extension
>> supports hardware updating of PTE A/D bits. This series enables Svade and
>> Svadu extensions for both host and guest OS.
>>
>> Regrading the mailing thread[1], we have 4 possible combinations of
>> these extensions in the device tree, the default hardware behavior for
>> these possibilities are:
>> 1) Neither Svade nor Svadu present in DT => It is technically
>>    unknown whether the platform uses Svade or Svadu. Supervisor
>>    software should be prepared to handle either hardware updating
>>    of the PTE A/D bits or page faults when they need updated.
>> 2) Only Svade present in DT => Supervisor must assume Svade to be
>>    always enabled.
>> 3) Only Svadu present in DT => Supervisor must assume Svadu to be
>>    always enabled.
>> 4) Both Svade and Svadu present in DT => Supervisor must assume
>>    Svadu turned-off at boot time. To use Svadu, supervisor must
>>    explicitly enable it using the SBI FWFT extension.
>>
>> The Svade extension is mandatory and the Svadu extension is optional in
>> RVA23 profile. Platforms want to take the advantage of Svadu can choose
>> 3. Those are aware of the profile can choose 4, and Linux won't get the
>> benefit of svadu until the SBI FWFT extension is available.
>>
>> [1] https://lore.kernel.org/linux-kernel/20240527-e9845c06619bca5cd285098c@orel/T/#m29644eb88e241ec282df4ccd5199514e913b06ee
>>
>> ---
>> v8:
>> - fix typo in PATCH1 (Samuel)
>> - use the new extension validating API in PATCH1 (Clément)
>> - update the dtbinding in PATCH2 (Samuel, Conor)
>> - add PATCH4 to fix compile error in get-reg-list test.
>>
>> v7:
>> - fix alignment in PATCH1
>> - update the dtbinding in PATCH2 (Conor, Jessica)
>>
>> v6:
>> - reflect the platform's behavior by riscv_isa_extension_available() and
>>   update the the arch_has_hw_pte_young() in PATCH1 (Conor, Andrew)
>> - update the dtbinding in PATCH2 (Alexandre, Andrew, Anup, Conor)
>> - update the henvcfg condition in PATCH3 (Andrew)
>> - check if Svade is allowed to disabled based on arch_has_hw_pte_young()
>>   in PATCH3
>>
>> v5:
>> - remove all Acked-by and Reviewed-by (Conor, Andrew)
>> - add Svade support
>> - update the arch_has_hw_pte_young() in PATCH1
>> - update the dtbinding in PATCH2 (Alexandre, Andrew)
>> - check the availibility of Svadu for Guest/VM based on
>>   arch_has_hw_pte_young() in PATCH3
>>
>> v4:
>> - fix 32bit kernel build error in PATCH1 (Conor)
>> - update the status of Svadu extension to ratified in PATCH2
>> - add the PATCH4 to suporrt SBI_FWFT_PTE_AD_HW_UPDATING for guest OS
>> - update the PATCH1 and PATCH3 to integrate with FWFT extension
>> - rebase PATCH5 on the lastest get-reg-list test (Andrew)
>>
>> v3:
>> - fix the control bit name to ADUE in PATCH1 and PATCH3
>> - update get-reg-list in PATCH4
>>
>> v2:
>> - add Co-developed-by: in PATCH1
>> - use riscv_has_extension_unlikely() to runtime patch the branch in PATCH1
>> - update dt-binding
>>
>> Yong-Xuan Wang (5):
>>   RISC-V: Add Svade and Svadu Extensions Support
>>   dt-bindings: riscv: Add Svade and Svadu Entries
>>   RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM
>>   KVM: riscv: selftests: Fix compile error
>>   KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list
>>     test
>>
>>  .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++
>>  arch/riscv/Kconfig                            |  1 +
>>  arch/riscv/include/asm/csr.h                  |  1 +
>>  arch/riscv/include/asm/hwcap.h                |  2 ++
>>  arch/riscv/include/asm/pgtable.h              | 13 ++++++++-
>>  arch/riscv/include/uapi/asm/kvm.h             |  2 ++
>>  arch/riscv/kernel/cpufeature.c                | 12 ++++++++
>>  arch/riscv/kvm/vcpu.c                         |  4 +++
>>  arch/riscv/kvm/vcpu_onereg.c                  | 15 ++++++++++
>>  .../selftests/kvm/riscv/get-reg-list.c        | 16 ++++++++---
>>  10 files changed, 89 insertions(+), 5 deletions(-)
>>
>> --
>> 2.17.1
>>
>>
>
> Let me know if this series can be taken through the KVM RISC-V tree.
> I can provide you with a shared tag as well.

I think the patchwork bot got confused by patch 4 going to fixes?  It 
says this was merged.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

if you still want to take it, otherwise just LMK and I'll pick it up.

> Regards,
> Anup

Re: [PATCH v8 0/5] Add Svade and Svadu Extensions Support

[Anup Patel]

On Fri, Sep 20, 2024 at 1:53 PM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> On Wed, 21 Aug 2024 07:43:20 PDT (-0700), anup@brainfault.org wrote:
> > Hi Palmer,
> >
> > On Fri, Jul 26, 2024 at 2:19 PM Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote:
> >>
> >> Svade and Svadu extensions represent two schemes for managing the PTE A/D
> >> bit. When the PTE A/D bits need to be set, Svade extension intdicates that
> >> a related page fault will be raised. In contrast, the Svadu extension
> >> supports hardware updating of PTE A/D bits. This series enables Svade and
> >> Svadu extensions for both host and guest OS.
> >>
> >> Regrading the mailing thread[1], we have 4 possible combinations of
> >> these extensions in the device tree, the default hardware behavior for
> >> these possibilities are:
> >> 1) Neither Svade nor Svadu present in DT => It is technically
> >>    unknown whether the platform uses Svade or Svadu. Supervisor
> >>    software should be prepared to handle either hardware updating
> >>    of the PTE A/D bits or page faults when they need updated.
> >> 2) Only Svade present in DT => Supervisor must assume Svade to be
> >>    always enabled.
> >> 3) Only Svadu present in DT => Supervisor must assume Svadu to be
> >>    always enabled.
> >> 4) Both Svade and Svadu present in DT => Supervisor must assume
> >>    Svadu turned-off at boot time. To use Svadu, supervisor must
> >>    explicitly enable it using the SBI FWFT extension.
> >>
> >> The Svade extension is mandatory and the Svadu extension is optional in
> >> RVA23 profile. Platforms want to take the advantage of Svadu can choose
> >> 3. Those are aware of the profile can choose 4, and Linux won't get the
> >> benefit of svadu until the SBI FWFT extension is available.
> >>
> >> [1] https://lore.kernel.org/linux-kernel/20240527-e9845c06619bca5cd285098c@orel/T/#m29644eb88e241ec282df4ccd5199514e913b06ee
> >>
> >> ---
> >> v8:
> >> - fix typo in PATCH1 (Samuel)
> >> - use the new extension validating API in PATCH1 (Clément)
> >> - update the dtbinding in PATCH2 (Samuel, Conor)
> >> - add PATCH4 to fix compile error in get-reg-list test.
> >>
> >> v7:
> >> - fix alignment in PATCH1
> >> - update the dtbinding in PATCH2 (Conor, Jessica)
> >>
> >> v6:
> >> - reflect the platform's behavior by riscv_isa_extension_available() and
> >>   update the the arch_has_hw_pte_young() in PATCH1 (Conor, Andrew)
> >> - update the dtbinding in PATCH2 (Alexandre, Andrew, Anup, Conor)
> >> - update the henvcfg condition in PATCH3 (Andrew)
> >> - check if Svade is allowed to disabled based on arch_has_hw_pte_young()
> >>   in PATCH3
> >>
> >> v5:
> >> - remove all Acked-by and Reviewed-by (Conor, Andrew)
> >> - add Svade support
> >> - update the arch_has_hw_pte_young() in PATCH1
> >> - update the dtbinding in PATCH2 (Alexandre, Andrew)
> >> - check the availibility of Svadu for Guest/VM based on
> >>   arch_has_hw_pte_young() in PATCH3
> >>
> >> v4:
> >> - fix 32bit kernel build error in PATCH1 (Conor)
> >> - update the status of Svadu extension to ratified in PATCH2
> >> - add the PATCH4 to suporrt SBI_FWFT_PTE_AD_HW_UPDATING for guest OS
> >> - update the PATCH1 and PATCH3 to integrate with FWFT extension
> >> - rebase PATCH5 on the lastest get-reg-list test (Andrew)
> >>
> >> v3:
> >> - fix the control bit name to ADUE in PATCH1 and PATCH3
> >> - update get-reg-list in PATCH4
> >>
> >> v2:
> >> - add Co-developed-by: in PATCH1
> >> - use riscv_has_extension_unlikely() to runtime patch the branch in PATCH1
> >> - update dt-binding
> >>
> >> Yong-Xuan Wang (5):
> >>   RISC-V: Add Svade and Svadu Extensions Support
> >>   dt-bindings: riscv: Add Svade and Svadu Entries
> >>   RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM
> >>   KVM: riscv: selftests: Fix compile error
> >>   KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list
> >>     test
> >>
> >>  .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++
> >>  arch/riscv/Kconfig                            |  1 +
> >>  arch/riscv/include/asm/csr.h                  |  1 +
> >>  arch/riscv/include/asm/hwcap.h                |  2 ++
> >>  arch/riscv/include/asm/pgtable.h              | 13 ++++++++-
> >>  arch/riscv/include/uapi/asm/kvm.h             |  2 ++
> >>  arch/riscv/kernel/cpufeature.c                | 12 ++++++++
> >>  arch/riscv/kvm/vcpu.c                         |  4 +++
> >>  arch/riscv/kvm/vcpu_onereg.c                  | 15 ++++++++++
> >>  .../selftests/kvm/riscv/get-reg-list.c        | 16 ++++++++---
> >>  10 files changed, 89 insertions(+), 5 deletions(-)
> >>
> >> --
> >> 2.17.1
> >>
> >>
> >
> > Let me know if this series can be taken through the KVM RISC-V tree.
> > I can provide you with a shared tag as well.
>
> I think the patchwork bot got confused by patch 4 going to fixes?  It
> says this was merged.
>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> if you still want to take it, otherwise just LMK and I'll pick it up.
>

I already sent KVM RISC-V PR for 6.12 which has been merged
as well. Please take this series (except PATCH4) through the
RISC-V tree.

Thanks,
Anup

Re: [PATCH v8 0/5] Add Svade and Svadu Extensions Support

[Anup Patel]

Hi Palmer,

On Fri, Sep 20, 2024 at 1:53 PM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> On Wed, 21 Aug 2024 07:43:20 PDT (-0700), anup@brainfault.org wrote:
> > Hi Palmer,
> >
> > On Fri, Jul 26, 2024 at 2:19 PM Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote:
> >>
> >> Svade and Svadu extensions represent two schemes for managing the PTE A/D
> >> bit. When the PTE A/D bits need to be set, Svade extension intdicates that
> >> a related page fault will be raised. In contrast, the Svadu extension
> >> supports hardware updating of PTE A/D bits. This series enables Svade and
> >> Svadu extensions for both host and guest OS.
> >>
> >> Regrading the mailing thread[1], we have 4 possible combinations of
> >> these extensions in the device tree, the default hardware behavior for
> >> these possibilities are:
> >> 1) Neither Svade nor Svadu present in DT => It is technically
> >>    unknown whether the platform uses Svade or Svadu. Supervisor
> >>    software should be prepared to handle either hardware updating
> >>    of the PTE A/D bits or page faults when they need updated.
> >> 2) Only Svade present in DT => Supervisor must assume Svade to be
> >>    always enabled.
> >> 3) Only Svadu present in DT => Supervisor must assume Svadu to be
> >>    always enabled.
> >> 4) Both Svade and Svadu present in DT => Supervisor must assume
> >>    Svadu turned-off at boot time. To use Svadu, supervisor must
> >>    explicitly enable it using the SBI FWFT extension.
> >>
> >> The Svade extension is mandatory and the Svadu extension is optional in
> >> RVA23 profile. Platforms want to take the advantage of Svadu can choose
> >> 3. Those are aware of the profile can choose 4, and Linux won't get the
> >> benefit of svadu until the SBI FWFT extension is available.
> >>
> >> [1] https://lore.kernel.org/linux-kernel/20240527-e9845c06619bca5cd285098c@orel/T/#m29644eb88e241ec282df4ccd5199514e913b06ee
> >>
> >> ---
> >> v8:
> >> - fix typo in PATCH1 (Samuel)
> >> - use the new extension validating API in PATCH1 (Clément)
> >> - update the dtbinding in PATCH2 (Samuel, Conor)
> >> - add PATCH4 to fix compile error in get-reg-list test.
> >>
> >> v7:
> >> - fix alignment in PATCH1
> >> - update the dtbinding in PATCH2 (Conor, Jessica)
> >>
> >> v6:
> >> - reflect the platform's behavior by riscv_isa_extension_available() and
> >>   update the the arch_has_hw_pte_young() in PATCH1 (Conor, Andrew)
> >> - update the dtbinding in PATCH2 (Alexandre, Andrew, Anup, Conor)
> >> - update the henvcfg condition in PATCH3 (Andrew)
> >> - check if Svade is allowed to disabled based on arch_has_hw_pte_young()
> >>   in PATCH3
> >>
> >> v5:
> >> - remove all Acked-by and Reviewed-by (Conor, Andrew)
> >> - add Svade support
> >> - update the arch_has_hw_pte_young() in PATCH1
> >> - update the dtbinding in PATCH2 (Alexandre, Andrew)
> >> - check the availibility of Svadu for Guest/VM based on
> >>   arch_has_hw_pte_young() in PATCH3
> >>
> >> v4:
> >> - fix 32bit kernel build error in PATCH1 (Conor)
> >> - update the status of Svadu extension to ratified in PATCH2
> >> - add the PATCH4 to suporrt SBI_FWFT_PTE_AD_HW_UPDATING for guest OS
> >> - update the PATCH1 and PATCH3 to integrate with FWFT extension
> >> - rebase PATCH5 on the lastest get-reg-list test (Andrew)
> >>
> >> v3:
> >> - fix the control bit name to ADUE in PATCH1 and PATCH3
> >> - update get-reg-list in PATCH4
> >>
> >> v2:
> >> - add Co-developed-by: in PATCH1
> >> - use riscv_has_extension_unlikely() to runtime patch the branch in PATCH1
> >> - update dt-binding
> >>
> >> Yong-Xuan Wang (5):
> >>   RISC-V: Add Svade and Svadu Extensions Support
> >>   dt-bindings: riscv: Add Svade and Svadu Entries
> >>   RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM
> >>   KVM: riscv: selftests: Fix compile error
> >>   KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list
> >>     test
> >>
> >>  .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++
> >>  arch/riscv/Kconfig                            |  1 +
> >>  arch/riscv/include/asm/csr.h                  |  1 +
> >>  arch/riscv/include/asm/hwcap.h                |  2 ++
> >>  arch/riscv/include/asm/pgtable.h              | 13 ++++++++-
> >>  arch/riscv/include/uapi/asm/kvm.h             |  2 ++
> >>  arch/riscv/kernel/cpufeature.c                | 12 ++++++++
> >>  arch/riscv/kvm/vcpu.c                         |  4 +++
> >>  arch/riscv/kvm/vcpu_onereg.c                  | 15 ++++++++++
> >>  .../selftests/kvm/riscv/get-reg-list.c        | 16 ++++++++---
> >>  10 files changed, 89 insertions(+), 5 deletions(-)
> >>
> >> --
> >> 2.17.1
> >>
> >>
> >
> > Let me know if this series can be taken through the KVM RISC-V tree.
> > I can provide you with a shared tag as well.
>
> I think the patchwork bot got confused by patch 4 going to fixes?  It
> says this was merged.
>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> if you still want to take it, otherwise just LMK and I'll pick it up.
>

I have queued this series for Linux-6.13

Thanks,
Anup

Re: [PATCH v8 0/5] Add Svade and Svadu Extensions Support

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (fixes)
by Anup Patel <anup@brainfault.org>:

On Fri, 26 Jul 2024 16:49:25 +0800 you wrote:
> Svade and Svadu extensions represent two schemes for managing the PTE A/D
> bit. When the PTE A/D bits need to be set, Svade extension intdicates that
> a related page fault will be raised. In contrast, the Svadu extension
> supports hardware updating of PTE A/D bits. This series enables Svade and
> Svadu extensions for both host and guest OS.
> 
> Regrading the mailing thread[1], we have 4 possible combinations of
> these extensions in the device tree, the default hardware behavior for
> these possibilities are:
> 1) Neither Svade nor Svadu present in DT => It is technically
>    unknown whether the platform uses Svade or Svadu. Supervisor
>    software should be prepared to handle either hardware updating
>    of the PTE A/D bits or page faults when they need updated.
> 2) Only Svade present in DT => Supervisor must assume Svade to be
>    always enabled.
> 3) Only Svadu present in DT => Supervisor must assume Svadu to be
>    always enabled.
> 4) Both Svade and Svadu present in DT => Supervisor must assume
>    Svadu turned-off at boot time. To use Svadu, supervisor must
>    explicitly enable it using the SBI FWFT extension.
> 
> [...]

Here is the summary with links:
  - [v8,1/5] RISC-V: Add Svade and Svadu Extensions Support
    https://git.kernel.org/riscv/c/94a7734d0967
  - [v8,2/5] dt-bindings: riscv: Add Svade and Svadu Entries
    https://git.kernel.org/riscv/c/b8d481671703
  - [v8,3/5] RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM
    https://git.kernel.org/riscv/c/97eccf7db4f2
  - [v8,4/5] KVM: riscv: selftests: Fix compile error
    (no matching commit)
  - [v8,5/5] KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test
    https://git.kernel.org/riscv/c/c74bfe4ffe8c

You are awesome, thank you!
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