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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id d5sm26108824wrs.21.2021.02.01.02.05.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Feb 2021 02:05:24 -0800 (PST) Subject: Re: [RFC 2/7] KVM: VMX: Expose IA32_PKRS MSR To: Chenyi Qiang , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , Xiaoyao Li Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20200807084841.7112-1-chenyi.qiang@intel.com> <20200807084841.7112-3-chenyi.qiang@intel.com> <62f5f5ba-cbe9-231d-365a-80a656208e37@redhat.com> From: Paolo Bonzini Message-ID: <192cfa2c-e54a-c7c1-30dd-7077e07e4af1@redhat.com> Date: Mon, 1 Feb 2021 11:05:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 01/02/21 10:53, Chenyi Qiang wrote: >>> >> >> Is the guest expected to do a lot of reads/writes to the MSR (e.g. at >> every context switch)? >> >> Even if this is the case, the MSR intercepts and the entry/exit >> controls should only be done if CR4.PKS=1.  If the guest does not use >> PKS, KVM should behave as if these patches did not exist. >> > > Hi Paolo, > > Per the MSR intercepts and entry/exit controls, IA32_PKRS access is > independent of the CR4.PKS bit, it just depends on CPUID enumeration. If > the guest doesn't set CR4.PKS but still has the CPUID capability, > modifying on PKRS should be supported but has no effect. IIUC, we can > not ignore these controls if CR4.PKS=0. Understood, I wanted to avoid paying the price (if any) of loading PKRS on vmentry and vmexit not just if CPUID.PKS=0, but also if CR4.PKS=0. If CR4.PKS=0 it would be nicer to enable the MSR intercept and disable the vmentry/vmexit controls; just run the guest with the host value of IA32_PKRS. Paolo