Re: [PATCH v9 01/10] x86/cpufeatures: Add support for L3 Smart Data Cache Injection Allocation Enforcement

[Reinette Chatre <reinette.chatre@intel.com>]

Hi Babu,

(Just highlighting some changelog formatting that was needed for ABMC
changelogs.)

On 9/2/25 3:41 PM, Babu Moger wrote:
> Smart Data Cache Injection (SDCI) is a mechanism that enables direct
> insertion of data from I/O devices into the L3 cache. By directly caching
> data from I/O devices rather than first storing the I/O data in DRAM,
> SDCI reduces demands on DRAM bandwidth and reduces latency to the processor
> consuming the I/O data.
> 
> The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software
> to control the portion of the L3 cache used for SDCI.
> 
> When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache
> partitions identified by the highest-supported L3_MASK_n register, where n
> is the maximum supported CLOSID.
> 
> Add CPUID feature bit that can be used to configure SDCIAE.
> 
> The SDCIAE feature details are documented in APM [1] available from [2].
> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
> Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
> Injection Allocation Enforcement (SDCIAE)

Compare with how indentation of ABMC "x86,fs/resctrl: Implement resctrl_arch_config_cntr()
to assign a counter with ABMC" was changed during merge. 

  [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
      Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
      Injection Allocation Enforcement (SDCIAE)

(also applies to patch #4)

> 
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]

Please place "Link:" tag at end to reduce needed adjustments during
merge.

> Signed-off-by: Babu Moger <babu.moger@amd.com>
> Acked-by: Borislav Petkov (AMD) <bp@alien8.de>
> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
> ---

Reinette