Re: [PATCH] report revision 3 of the ACPI/SMBus PIIX4 controller

[Marcelo Tosatti <marcelo-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org>]

On Sun, Jan 13, 2008 at 12:19:20PM +0100, Anders wrote:
> Marcelo Tosatti <marcelo-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org> writes:
> 
> > This reduces idle guest CPU consumption from 14% to 8% on 4-way KVM
> > guest.
> 
> How do you get that high consumption? What combination of clocks/hz on
> host/guest are you using?

CONFIG_HZ=250

4-way SMP guest, 8-way Intel host (without the VMX TSC sync patch posted
previously).

> I am cursious, since my idle KVM process is at less than 1%.

You have an UP guest right?

The problem is that the TSC synchronization check on boot is
only performed on SMP guests. Intel hosts usually have their TSC
synchronized, whereas AMD ones don't, so they fall back to use the ACPI
PM timer (until the HPET QEMU/KVM support is in place).

UP guests use TSC as a clocksource by default, and TSC reads won't cause
a VMExit.


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