From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Yang, Sheng" Subject: [RFC][PATCH 2/7] KVM: Common interface of TLP and feature detection for EPT Date: Fri, 1 Feb 2008 16:22:10 +0800 Message-ID: <200802011622.10442.sheng.yang@intel.com> Mime-Version: 1.0 Content-Type: Multipart/Mixed; boundary="Boundary-00=_yatoHKxe+ALPJUX" Cc: kvm-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org To: Avi Kivity Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org Errors-To: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: kvm.vger.kernel.org --Boundary-00=_yatoHKxe+ALPJUX Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline =46rom e5ed046f6862a9e314f334458d46f871b7fb8b58 Mon Sep 17 00:00:00 2001 =46rom: Sheng Yang Date: Fri, 1 Feb 2008 06:32:17 +0800 Subject: [PATCH] KVM: Common interface of TLP and feature detection for EPT The patch export tlp_enabled() from kvm_x86_ops as common interface, and make the feature detection ready for EPT. Signed-off-by: Sheng Yang =2D-- arch/x86/kvm/svm.c | 6 +++ arch/x86/kvm/vmx.c | 88 ++++++++++++++++++++++++++++++++++++++++= +-- arch/x86/kvm/vmx.h | 26 +++++++++++++ include/asm-x86/kvm_host.h | 4 ++ 4 files changed, 119 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index d1c7fcb..c43f0cc 100644 =2D-- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -1662,6 +1662,11 @@ static bool svm_cpu_has_accelerated_tpr(void) return false; } +static int svm_tlp_enabled(void) +{ + return 0; +} + static struct kvm_x86_ops svm_x86_ops =3D { .cpu_has_kvm_support =3D has_svm, .disabled_by_bios =3D is_disabled, @@ -1718,6 +1723,7 @@ static struct kvm_x86_ops svm_x86_ops =3D { .inject_pending_vectors =3D do_interrupt_requests, .set_tss_addr =3D svm_set_tss_addr, + .tlp_enabled =3D svm_tlp_enabled, }; static int __init svm_init(void) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 3d8949a..5f3767a 100644 =2D-- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -40,12 +40,31 @@ module_param(bypass_guest_pf, bool, 0); static int enable_vpid =3D 1; module_param(enable_vpid, bool, 0); +static int enable_ept =3D 0; +module_param(enable_ept, bool, 0); + struct vmcs { u32 revision_id; u32 abort; char data[0]; }; +typedef union { + struct { + u64 r : 1, + w : 1, + x : 1, + emt : 3, + rsvd_igmt : 1, + sp_avail : 1, + avail1 : 4, + addr_mfn : 45, + rsvd : 5, + avail2 : 2; + } fields; + u64 entry; +} epte_t; + struct vcpu_vmx { struct kvm_vcpu vcpu; int launched; @@ -104,6 +123,11 @@ static struct vmcs_config { u32 vmentry_ctrl; } vmcs_config; +struct vmx_capability { + u32 ept; + u32 vpid; +} vmx_capability; + #define VMX_SEGMENT_FIELD(seg) \ [VCPU_SREG_##seg] =3D { \ .selector =3D GUEST_##seg##_SELECTOR, \ @@ -217,6 +241,35 @@ static inline int cpu_has_vmx_vpid(void) SECONDARY_EXEC_ENABLE_VPID); } +static inline int cpu_has_vmx_invept_individual_addr(void) +{ + return (!!(vmx_capability.ept & (1u<<24))); +} + +static inline int cpu_has_vmx_invept_context(void) +{ + return (!!(vmx_capability.ept & (1u<<25))); +} + +static inline int cpu_has_vmx_invept_global(void) +{ + return (!!(vmx_capability.ept & (1u<<26))); +} + +static inline int cpu_has_vmx_ept(void) +{ + return (vmcs_config.cpu_based_2nd_exec_ctrl & + SECONDARY_EXEC_ENABLE_EPT); +} + +static int vm_need_ept(void) +{ + if (cpu_has_vmx_ept() && enable_ept) + return KVM_TLP_EPT; + else + return 0; +} + static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) { int i; @@ -975,7 +1028,7 @@ static __init int adjust_vmx_controls(u32 ctl_min, u32= =20 ctl_opt, static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) { u32 vmx_msr_low, vmx_msr_high; =2D u32 min, opt; + u32 min, opt, min2, opt2; u32 _pin_based_exec_control =3D 0; u32 _cpu_based_exec_control =3D 0; u32 _cpu_based_2nd_exec_control =3D 0; @@ -993,6 +1046,8 @@ static __init int setup_vmcs_config(struct vmcs_config= =20 *vmcs_conf) CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | #endif + CPU_BASED_CR3_LOAD_EXITING | + CPU_BASED_CR3_STORE_EXITING | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MOV_DR_EXITING | CPU_BASED_USE_TSC_OFFSETING; @@ -1007,11 +1062,13 @@ static __init int setup_vmcs_config(struct vmcs_con= fig=20 *vmcs_conf) ~CPU_BASED_CR8_STORE_EXITING; #endif if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { =2D min =3D 0; =2D opt =3D SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | + min2 =3D 0; + opt2 =3D SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | SECONDARY_EXEC_WBINVD_EXITING | =2D SECONDARY_EXEC_ENABLE_VPID; =2D if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2, + SECONDARY_EXEC_ENABLE_VPID | + SECONDARY_EXEC_ENABLE_EPT; + if (adjust_vmx_controls(min2, opt2, + MSR_IA32_VMX_PROCBASED_CTLS2, &_cpu_based_2nd_exec_control) < 0) return -EIO; } @@ -1020,6 +1077,16 @@ static __init int setup_vmcs_config(struct vmcs_conf= ig=20 *vmcs_conf) SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) _cpu_based_exec_control &=3D ~CPU_BASED_TPR_SHADOW; #endif + if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { + /* CR3 accesses don't need to cause VMExits in EPT */ + min &=3D ~(CPU_BASED_CR3_LOAD_EXITING | + CPU_BASED_CR3_STORE_EXITING); + if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, + &_cpu_based_exec_control) < 0) + return -EIO; + rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, + vmx_capability.ept, vmx_capability.vpid); + } min =3D 0; #ifdef CONFIG_X86_64 @@ -1582,6 +1649,9 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx) CPU_BASED_CR8_LOAD_EXITING; #endif } + if (!vm_need_ept()) + exec_control |=3D CPU_BASED_CR3_LOAD_EXITING | + CPU_BASED_CR3_STORE_EXITING; vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); if (cpu_has_secondary_exec_ctrls()) { @@ -1591,6 +1661,8 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx) ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; if (vmx->vpid =3D=3D 0) exec_control &=3D ~SECONDARY_EXEC_ENABLE_VPID; + if (!vm_need_ept()) + exec_control &=3D ~SECONDARY_EXEC_ENABLE_EPT; vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); } @@ -1765,6 +1837,11 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); + if (vm_need_ept()) { + vmcs_write64(EPT_POINTER, vmx->vcpu.kvm->arch.eptp.entry); + printk(KERN_INFO "EPT Enabled, eptp is 0x%lx\n", + (long unsigned int)vmx->vcpu.kvm->arch.eptp.entry); + } if (vmx->vpid !=3D 0) vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); @@ -2688,6 +2765,7 @@ static struct kvm_x86_ops vmx_x86_ops =3D { .inject_pending_vectors =3D do_interrupt_requests, .set_tss_addr =3D vmx_set_tss_addr, + .tlp_enabled =3D vm_need_ept, }; static int __init vmx_init(void) diff --git a/arch/x86/kvm/vmx.h b/arch/x86/kvm/vmx.h index 436ce0f..e2ee50b 100644 =2D-- a/arch/x86/kvm/vmx.h +++ b/arch/x86/kvm/vmx.h @@ -35,6 +35,8 @@ #define CPU_BASED_MWAIT_EXITING 0x00000400 #define CPU_BASED_RDPMC_EXITING 0x00000800 #define CPU_BASED_RDTSC_EXITING 0x00001000 +#define CPU_BASED_CR3_LOAD_EXITING 0x00008000 +#define CPU_BASED_CR3_STORE_EXITING 0x00010000 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000 #define CPU_BASED_CR8_STORE_EXITING 0x00100000 #define CPU_BASED_TPR_SHADOW 0x00200000 @@ -49,6 +51,7 @@ * Definitions of Secondary Processor-Based VM-Execution Controls. */ #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 +#define SECONDARY_EXEC_ENABLE_EPT 0x00000002 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 @@ -100,10 +103,22 @@ enum vmcs_field { VIRTUAL_APIC_PAGE_ADDR_HIGH =3D 0x00002013, APIC_ACCESS_ADDR =3D 0x00002014, APIC_ACCESS_ADDR_HIGH =3D 0x00002015, + EPT_POINTER =3D 0x0000201a, + EPT_POINTER_HIGH =3D 0x0000201b, + GUEST_PHYSICAL_ADDRESS =3D 0x00002400, + GUEST_PHYSICAL_ADDRESS_HIGH =3D 0x00002401, VMCS_LINK_POINTER =3D 0x00002800, VMCS_LINK_POINTER_HIGH =3D 0x00002801, GUEST_IA32_DEBUGCTL =3D 0x00002802, GUEST_IA32_DEBUGCTL_HIGH =3D 0x00002803, + GUEST_PDPTR0 =3D 0x0000280a, + GUEST_PDPTR0_HIGH =3D 0x0000280b, + GUEST_PDPTR1 =3D 0x0000280c, + GUEST_PDPTR1_HIGH =3D 0x0000280d, + GUEST_PDPTR2 =3D 0x0000280e, + GUEST_PDPTR2_HIGH =3D 0x0000280f, + GUEST_PDPTR3 =3D 0x00002810, + GUEST_PDPTR3_HIGH =3D 0x00002811, PIN_BASED_VM_EXEC_CONTROL =3D 0x00004000, CPU_BASED_VM_EXEC_CONTROL =3D 0x00004002, EXCEPTION_BITMAP =3D 0x00004004, @@ -226,6 +241,8 @@ enum vmcs_field { #define EXIT_REASON_MWAIT_INSTRUCTION 36 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43 #define EXIT_REASON_APIC_ACCESS 44 +#define EXIT_REASON_EPT_VIOLATION 48 +#define EXIT_REASON_EPT_MISCONFIG 49 #define EXIT_REASON_WBINVD 54 /* @@ -316,6 +333,7 @@ enum vmcs_field { #define MSR_IA32_VMX_CR4_FIXED1 0x489 #define MSR_IA32_VMX_VMCS_ENUM 0x48a #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b +#define MSR_IA32_VMX_EPT_VPID_CAP 0x48c #define MSR_IA32_FEATURE_CONTROL 0x3a #define MSR_IA32_FEATURE_CONTROL_LOCKED 0x1 @@ -327,4 +345,12 @@ enum vmcs_field { #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1 #define VMX_VPID_EXTENT_ALL_CONTEXT 2 +#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xCF000UL +#define VMX_EPT_MAX_GAW 0x4 +#define VMX_EPT_DEFAULT_MT 0x6 +#define VMX_EPT_DEFAULT_GAW 0x3 +#define VMX_EPT_EXTENT_INDIVIDUAL_ADDR 0 +#define VMX_EPT_EXTENT_CONTEXT 1 +#define VMX_EPT_EXTENT_GLOBAL 2 + #endif diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h index f6028c6..c1d52af 100644 =2D-- a/include/asm-x86/kvm_host.h +++ b/include/asm-x86/kvm_host.h @@ -407,6 +407,7 @@ struct kvm_x86_ops { struct kvm_run *run); int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); + int (*tlp_enabled)(void); /* Two Level Paging */ }; extern struct kvm_x86_ops *kvm_x86_ops; @@ -615,6 +616,7 @@ static inline void kvm_inject_gp(struct kvm_vcpu *vcpu,= =20 u32 error_code) #define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4" #define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4" #define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30" +#define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08" #define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08" #define MSR_IA32_TIME_STAMP_COUNTER 0x010 @@ -625,4 +627,6 @@ static inline void kvm_inject_gp(struct kvm_vcpu *vcpu,= =20 u32 error_code) #define TSS_REDIRECTION_SIZE (256 / 8) #define RMODE_TSS_SIZE (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SI= ZE=20 + 1) +#define KVM_TLP_EPT 0x1 + #endif =2D- debian.1.5.3.7.1-dirty --Boundary-00=_yatoHKxe+ALPJUX Content-Type: text/x-diff; charset="utf-8"; name="0002-KVM-Common-interface-of-TLP-and-feature-detection-f.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="0002-KVM-Common-interface-of-TLP-and-feature-detection-f.patch" =46rom e5ed046f6862a9e314f334458d46f871b7fb8b58 Mon Sep 17 00:00:00 2001 =46rom: Sheng Yang Date: Fri, 1 Feb 2008 06:32:17 +0800 Subject: [PATCH] KVM: Common interface of TLP and feature detection for EPT The patch export tlp_enabled() from kvm_x86_ops as common interface, and make the feature detection ready for EPT. Signed-off-by: Sheng Yang =2D-- arch/x86/kvm/svm.c | 6 +++ arch/x86/kvm/vmx.c | 88 ++++++++++++++++++++++++++++++++++++++++= +-- arch/x86/kvm/vmx.h | 26 +++++++++++++ include/asm-x86/kvm_host.h | 4 ++ 4 files changed, 119 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index d1c7fcb..c43f0cc 100644 =2D-- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -1662,6 +1662,11 @@ static bool svm_cpu_has_accelerated_tpr(void) return false; } =20 +static int svm_tlp_enabled(void) +{ + return 0; +} + static struct kvm_x86_ops svm_x86_ops =3D { .cpu_has_kvm_support =3D has_svm, .disabled_by_bios =3D is_disabled, @@ -1718,6 +1723,7 @@ static struct kvm_x86_ops svm_x86_ops =3D { .inject_pending_vectors =3D do_interrupt_requests, =20 .set_tss_addr =3D svm_set_tss_addr, + .tlp_enabled =3D svm_tlp_enabled, }; =20 static int __init svm_init(void) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 3d8949a..5f3767a 100644 =2D-- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -40,12 +40,31 @@ module_param(bypass_guest_pf, bool, 0); static int enable_vpid =3D 1; module_param(enable_vpid, bool, 0); =20 +static int enable_ept =3D 0; +module_param(enable_ept, bool, 0); + struct vmcs { u32 revision_id; u32 abort; char data[0]; }; =20 +typedef union { + struct { + u64 r : 1, + w : 1, + x : 1, + emt : 3, + rsvd_igmt : 1, + sp_avail : 1, + avail1 : 4, + addr_mfn : 45, + rsvd : 5, + avail2 : 2; + } fields; + u64 entry; +} epte_t; + struct vcpu_vmx { struct kvm_vcpu vcpu; int launched; @@ -104,6 +123,11 @@ static struct vmcs_config { u32 vmentry_ctrl; } vmcs_config; =20 +struct vmx_capability { + u32 ept; + u32 vpid; +} vmx_capability; + #define VMX_SEGMENT_FIELD(seg) \ [VCPU_SREG_##seg] =3D { \ .selector =3D GUEST_##seg##_SELECTOR, \ @@ -217,6 +241,35 @@ static inline int cpu_has_vmx_vpid(void) SECONDARY_EXEC_ENABLE_VPID); } =20 +static inline int cpu_has_vmx_invept_individual_addr(void) +{ + return (!!(vmx_capability.ept & (1u<<24))); +} + +static inline int cpu_has_vmx_invept_context(void) +{ + return (!!(vmx_capability.ept & (1u<<25))); +} + +static inline int cpu_has_vmx_invept_global(void) +{ + return (!!(vmx_capability.ept & (1u<<26))); +} + +static inline int cpu_has_vmx_ept(void) +{ + return (vmcs_config.cpu_based_2nd_exec_ctrl & + SECONDARY_EXEC_ENABLE_EPT); +} + +static int vm_need_ept(void) +{ + if (cpu_has_vmx_ept() && enable_ept) + return KVM_TLP_EPT; + else + return 0; +} + static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) { int i; @@ -975,7 +1028,7 @@ static __init int adjust_vmx_controls(u32 ctl_min, u32= ctl_opt, static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) { u32 vmx_msr_low, vmx_msr_high; =2D u32 min, opt; + u32 min, opt, min2, opt2; u32 _pin_based_exec_control =3D 0; u32 _cpu_based_exec_control =3D 0; u32 _cpu_based_2nd_exec_control =3D 0; @@ -993,6 +1046,8 @@ static __init int setup_vmcs_config(struct vmcs_config= *vmcs_conf) CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | #endif + CPU_BASED_CR3_LOAD_EXITING | + CPU_BASED_CR3_STORE_EXITING | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MOV_DR_EXITING | CPU_BASED_USE_TSC_OFFSETING; @@ -1007,11 +1062,13 @@ static __init int setup_vmcs_config(struct vmcs_con= fig *vmcs_conf) ~CPU_BASED_CR8_STORE_EXITING; #endif if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { =2D min =3D 0; =2D opt =3D SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | + min2 =3D 0; + opt2 =3D SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | SECONDARY_EXEC_WBINVD_EXITING | =2D SECONDARY_EXEC_ENABLE_VPID; =2D if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2, + SECONDARY_EXEC_ENABLE_VPID | + SECONDARY_EXEC_ENABLE_EPT; + if (adjust_vmx_controls(min2, opt2, + MSR_IA32_VMX_PROCBASED_CTLS2, &_cpu_based_2nd_exec_control) < 0) return -EIO; } @@ -1020,6 +1077,16 @@ static __init int setup_vmcs_config(struct vmcs_conf= ig *vmcs_conf) SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) _cpu_based_exec_control &=3D ~CPU_BASED_TPR_SHADOW; #endif + if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { + /* CR3 accesses don't need to cause VMExits in EPT */ + min &=3D ~(CPU_BASED_CR3_LOAD_EXITING | + CPU_BASED_CR3_STORE_EXITING); + if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, + &_cpu_based_exec_control) < 0) + return -EIO; + rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, + vmx_capability.ept, vmx_capability.vpid); + } =20 min =3D 0; #ifdef CONFIG_X86_64 @@ -1582,6 +1649,9 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx) CPU_BASED_CR8_LOAD_EXITING; #endif } + if (!vm_need_ept()) + exec_control |=3D CPU_BASED_CR3_LOAD_EXITING | + CPU_BASED_CR3_STORE_EXITING; vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); =20 if (cpu_has_secondary_exec_ctrls()) { @@ -1591,6 +1661,8 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx) ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; if (vmx->vpid =3D=3D 0) exec_control &=3D ~SECONDARY_EXEC_ENABLE_VPID; + if (!vm_need_ept()) + exec_control &=3D ~SECONDARY_EXEC_ENABLE_EPT; vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); } =20 @@ -1765,6 +1837,11 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); + if (vm_need_ept()) { + vmcs_write64(EPT_POINTER, vmx->vcpu.kvm->arch.eptp.entry); + printk(KERN_INFO "EPT Enabled, eptp is 0x%lx\n", + (long unsigned int)vmx->vcpu.kvm->arch.eptp.entry); + } =20 if (vmx->vpid !=3D 0) vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); @@ -2688,6 +2765,7 @@ static struct kvm_x86_ops vmx_x86_ops =3D { .inject_pending_vectors =3D do_interrupt_requests, =20 .set_tss_addr =3D vmx_set_tss_addr, + .tlp_enabled =3D vm_need_ept, }; =20 static int __init vmx_init(void) diff --git a/arch/x86/kvm/vmx.h b/arch/x86/kvm/vmx.h index 436ce0f..e2ee50b 100644 =2D-- a/arch/x86/kvm/vmx.h +++ b/arch/x86/kvm/vmx.h @@ -35,6 +35,8 @@ #define CPU_BASED_MWAIT_EXITING 0x00000400 #define CPU_BASED_RDPMC_EXITING 0x00000800 #define CPU_BASED_RDTSC_EXITING 0x00001000 +#define CPU_BASED_CR3_LOAD_EXITING 0x00008000 +#define CPU_BASED_CR3_STORE_EXITING 0x00010000 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000 #define CPU_BASED_CR8_STORE_EXITING 0x00100000 #define CPU_BASED_TPR_SHADOW 0x00200000 @@ -49,6 +51,7 @@ * Definitions of Secondary Processor-Based VM-Execution Controls. */ #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 +#define SECONDARY_EXEC_ENABLE_EPT 0x00000002 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 =20 @@ -100,10 +103,22 @@ enum vmcs_field { VIRTUAL_APIC_PAGE_ADDR_HIGH =3D 0x00002013, APIC_ACCESS_ADDR =3D 0x00002014, APIC_ACCESS_ADDR_HIGH =3D 0x00002015, + EPT_POINTER =3D 0x0000201a, + EPT_POINTER_HIGH =3D 0x0000201b, + GUEST_PHYSICAL_ADDRESS =3D 0x00002400, + GUEST_PHYSICAL_ADDRESS_HIGH =3D 0x00002401, VMCS_LINK_POINTER =3D 0x00002800, VMCS_LINK_POINTER_HIGH =3D 0x00002801, GUEST_IA32_DEBUGCTL =3D 0x00002802, GUEST_IA32_DEBUGCTL_HIGH =3D 0x00002803, + GUEST_PDPTR0 =3D 0x0000280a, + GUEST_PDPTR0_HIGH =3D 0x0000280b, + GUEST_PDPTR1 =3D 0x0000280c, + GUEST_PDPTR1_HIGH =3D 0x0000280d, + GUEST_PDPTR2 =3D 0x0000280e, + GUEST_PDPTR2_HIGH =3D 0x0000280f, + GUEST_PDPTR3 =3D 0x00002810, + GUEST_PDPTR3_HIGH =3D 0x00002811, PIN_BASED_VM_EXEC_CONTROL =3D 0x00004000, CPU_BASED_VM_EXEC_CONTROL =3D 0x00004002, EXCEPTION_BITMAP =3D 0x00004004, @@ -226,6 +241,8 @@ enum vmcs_field { #define EXIT_REASON_MWAIT_INSTRUCTION 36 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43 #define EXIT_REASON_APIC_ACCESS 44 +#define EXIT_REASON_EPT_VIOLATION 48 +#define EXIT_REASON_EPT_MISCONFIG 49 #define EXIT_REASON_WBINVD 54 =20 /* @@ -316,6 +333,7 @@ enum vmcs_field { #define MSR_IA32_VMX_CR4_FIXED1 0x489 #define MSR_IA32_VMX_VMCS_ENUM 0x48a #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b +#define MSR_IA32_VMX_EPT_VPID_CAP 0x48c =20 #define MSR_IA32_FEATURE_CONTROL 0x3a #define MSR_IA32_FEATURE_CONTROL_LOCKED 0x1 @@ -327,4 +345,12 @@ enum vmcs_field { #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1 #define VMX_VPID_EXTENT_ALL_CONTEXT 2 =20 +#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xCF000UL +#define VMX_EPT_MAX_GAW 0x4 +#define VMX_EPT_DEFAULT_MT 0x6 +#define VMX_EPT_DEFAULT_GAW 0x3 +#define VMX_EPT_EXTENT_INDIVIDUAL_ADDR 0 +#define VMX_EPT_EXTENT_CONTEXT 1 +#define VMX_EPT_EXTENT_GLOBAL 2 + #endif diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h index f6028c6..c1d52af 100644 =2D-- a/include/asm-x86/kvm_host.h +++ b/include/asm-x86/kvm_host.h @@ -407,6 +407,7 @@ struct kvm_x86_ops { struct kvm_run *run); =20 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); + int (*tlp_enabled)(void); /* Two Level Paging */ }; =20 extern struct kvm_x86_ops *kvm_x86_ops; @@ -615,6 +616,7 @@ static inline void kvm_inject_gp(struct kvm_vcpu *vcpu,= u32 error_code) #define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4" #define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4" #define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30" +#define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08" #define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08" =20 #define MSR_IA32_TIME_STAMP_COUNTER 0x010 @@ -625,4 +627,6 @@ static inline void kvm_inject_gp(struct kvm_vcpu *vcpu,= u32 error_code) #define TSS_REDIRECTION_SIZE (256 / 8) #define RMODE_TSS_SIZE (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SI= ZE + 1) =20 +#define KVM_TLP_EPT 0x1 + #endif =2D-=20 debian.1.5.3.7.1-dirty --Boundary-00=_yatoHKxe+ALPJUX Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline ------------------------------------------------------------------------- This SF.net email is sponsored by: Microsoft Defy all challenges. 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