KVM: SVM: Implement LBRV virtualization

KVM: SVM: Implement LBRV virtualization

[Joerg Roedel]

This little patchset implements virtualization of the Last Branch Record
feature (LBRV) into the KVM-AMD module where this is available in hardware. For
every non-LBRV capable hardware it only enables access to the 5 LBR MSRs. Without
this access Windows XP 64 bit crashes in the installation routine.

Joerg

diffstat:

 arch/x86/kvm/kvm_svm.h |    2 +
 arch/x86/kvm/svm.c     |  125 ++++++++++++++++++++++++++++++++----------------
 2 files changed, 86 insertions(+), 41 deletions(-)





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[PATCH 1/3] KVM: SVM: let init_vmcb() take struct vcpu_svm as parameter

[Joerg Roedel]

Change the parameter of the init_vmcb() function in the kvm-amd module from
struct vmcb to struct vcpu_svm.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Markus Rechberger <markus.rechberger@amd.com>
---
 arch/x86/kvm/svm.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 13765e9..6e0c6bd 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -471,10 +471,10 @@ static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 	seg->base = 0;
 }
 
-static void init_vmcb(struct vmcb *vmcb)
+static void init_vmcb(struct vcpu_svm *svm)
 {
-	struct vmcb_control_area *control = &vmcb->control;
-	struct vmcb_save_area *save = &vmcb->save;
+	struct vmcb_control_area *control = &svm->vmcb->control;
+	struct vmcb_save_area *save = &svm->vmcb->save;
 
 	control->intercept_cr_read = 	INTERCEPT_CR0_MASK |
 					INTERCEPT_CR3_MASK |
@@ -600,7 +600,7 @@ static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
 
-	init_vmcb(svm->vmcb);
+	init_vmcb(svm);
 
 	if (vcpu->vcpu_id != 0) {
 		svm->vmcb->save.rip = 0;
@@ -638,7 +638,7 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 	svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 	svm->asid_generation = 0;
 	memset(svm->db_regs, 0, sizeof(svm->db_regs));
-	init_vmcb(svm->vmcb);
+	init_vmcb(svm);
 
 	fx_init(&svm->vcpu);
 	svm->vcpu.fpu_active = 1;
@@ -1024,7 +1024,7 @@ static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 	 * so reinitialize it.
 	 */
 	clear_page(svm->vmcb);
-	init_vmcb(svm->vmcb);
+	init_vmcb(svm);
 
 	kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
 	return 0;
-- 
1.5.3.7




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[PATCH 2/3] KVM: SVM: allocate the MSR permission map per VCPU

[Joerg Roedel]

This patch changes the kvm-amd module to allocate the SVM MSR permission map
per VCPU instead of a global map for all VCPUs. With this we have more
flexibility allowing specific guests to access virtualized MSRs. This is
required for LBRV virtualization.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Markus Rechberger <markus.rechberger@amd.com>
---
 arch/x86/kvm/kvm_svm.h |    2 +
 arch/x86/kvm/svm.c     |   67 +++++++++++++++++++++++-------------------------
 2 files changed, 34 insertions(+), 35 deletions(-)

diff --git a/arch/x86/kvm/kvm_svm.h b/arch/x86/kvm/kvm_svm.h
index ecdfe97..65ef0fc 100644
--- a/arch/x86/kvm/kvm_svm.h
+++ b/arch/x86/kvm/kvm_svm.h
@@ -39,6 +39,8 @@ struct vcpu_svm {
 	unsigned long host_db_regs[NUM_DB_REGS];
 	unsigned long host_dr6;
 	unsigned long host_dr7;
+
+	u32 *msrpm;
 };
 
 #endif
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 6e0c6bd..50ee223 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -65,7 +65,6 @@ static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 }
 
 unsigned long iopm_base;
-unsigned long msrpm_base;
 
 struct kvm_ldttss_desc {
 	u16 limit0;
@@ -370,12 +369,29 @@ static void set_msr_interception(u32 *msrpm, unsigned msr,
 	BUG();
 }
 
+static void svm_vcpu_init_msrpm(u32 *msrpm)
+{
+	memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
+
+#ifdef CONFIG_X86_64
+	set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
+	set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
+	set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
+	set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
+	set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
+	set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
+#endif
+	set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
+	set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
+	set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
+	set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
+}
+
 static __init int svm_hardware_setup(void)
 {
 	int cpu;
 	struct page *iopm_pages;
-	struct page *msrpm_pages;
-	void *iopm_va, *msrpm_va;
+	void *iopm_va;
 	int r;
 
 	iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
@@ -388,37 +404,13 @@ static __init int svm_hardware_setup(void)
 	clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 	iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 
-
-	msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
-
-	r = -ENOMEM;
-	if (!msrpm_pages)
-		goto err_1;
-
-	msrpm_va = page_address(msrpm_pages);
-	memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
-	msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
-
-#ifdef CONFIG_X86_64
-	set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
-	set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
-	set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
-	set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
-	set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
-	set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
-#endif
-	set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
-	set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
-	set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
-	set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
-
 	if (boot_cpu_has(X86_FEATURE_NX))
 		kvm_enable_efer_bits(EFER_NX);
 
 	for_each_online_cpu(cpu) {
 		r = svm_cpu_init(cpu);
 		if (r)
-			goto err_2;
+			goto err;
 	}
 
 	svm_features = cpuid_edx(SVM_CPUID_FUNC);
@@ -438,10 +430,7 @@ static __init int svm_hardware_setup(void)
 
 	return 0;
 
-err_2:
-	__free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
-	msrpm_base = 0;
-err_1:
+err:
 	__free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 	iopm_base = 0;
 	return r;
@@ -449,9 +438,8 @@ err_1:
 
 static __exit void svm_hardware_unsetup(void)
 {
-	__free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
 	__free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
-	iopm_base = msrpm_base = 0;
+	iopm_base = 0;
 }
 
 static void init_seg(struct vmcb_seg *seg)
@@ -536,7 +524,7 @@ static void init_vmcb(struct vcpu_svm *svm)
 				(1ULL << INTERCEPT_MWAIT);
 
 	control->iopm_base_pa = iopm_base;
-	control->msrpm_base_pa = msrpm_base;
+	control->msrpm_base_pa = __pa(svm->msrpm);
 	control->tsc_offset = 0;
 	control->int_ctl = V_INTR_MASKING_MASK;
 
@@ -615,6 +603,7 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 {
 	struct vcpu_svm *svm;
 	struct page *page;
+	struct page *msrpm_pages;
 	int err;
 
 	svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
@@ -633,6 +622,13 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 		goto uninit;
 	}
 
+	err = -ENOMEM;
+	msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
+	if (!msrpm_pages)
+		goto uninit;
+	svm->msrpm = page_address(msrpm_pages);
+	svm_vcpu_init_msrpm(svm->msrpm);
+
 	svm->vmcb = page_address(page);
 	clear_page(svm->vmcb);
 	svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
@@ -661,6 +657,7 @@ static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 	struct vcpu_svm *svm = to_svm(vcpu);
 
 	__free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
+	__free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 	kvm_vcpu_uninit(vcpu);
 	kmem_cache_free(kvm_vcpu_cache, svm);
 }
-- 
1.5.3.7




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[PATCH 3/3] KVM: SVM: enable LBRV virtualization

[Joerg Roedel]

This patch implements the Last Branch Record Virtualization (LBRV) feature of
the AMD Barcelona and Phenom processors into the kvm-amd module. It will only
be enabled if the guest enables last branch recording in the DEBUG_CTL MSR. It
also gives the guest access to the according MSRs which fixes the installation
of Windows XP 64 bit on SVM.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Markus Rechberger <markus.rechberger@amd.com>
---
 arch/x86/kvm/svm.c |   46 ++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 46 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 50ee223..2a71491 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -387,6 +387,28 @@ static void svm_vcpu_init_msrpm(u32 *msrpm)
 	set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 }
 
+static void svm_enable_lbrv(struct vcpu_svm *svm)
+{
+	u32 *msrpm = svm->msrpm;
+
+	svm->vmcb->control.lbr_ctl = 1;
+	set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
+	set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
+	set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
+	set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
+}
+
+static void svm_disable_lbrv(struct vcpu_svm *svm)
+{
+	u32 *msrpm = svm->msrpm;
+
+	svm->vmcb->control.lbr_ctl = 0;
+	set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
+	set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
+	set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
+	set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
+}
+
 static __init int svm_hardware_setup(void)
 {
 	int cpu;
@@ -1152,6 +1174,21 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
 	case MSR_IA32_SYSENTER_ESP:
 		*data = svm->vmcb->save.sysenter_esp;
 		break;
+	case MSR_IA32_DEBUGCTLMSR:
+		*data = svm->vmcb->save.dbgctl;
+		break;
+	case MSR_IA32_LASTBRANCHFROMIP:
+		*data = svm->vmcb->save.br_from;
+		break;
+	case MSR_IA32_LASTBRANCHTOIP:
+		*data = svm->vmcb->save.br_to;
+		break;
+	case MSR_IA32_LASTINTFROMIP:
+		*data = svm->vmcb->save.last_excp_from;
+		break;
+	case MSR_IA32_LASTINTTOIP:
+		*data = svm->vmcb->save.last_excp_to;
+		break;
 	default:
 		return kvm_get_msr_common(vcpu, ecx, data);
 	}
@@ -1224,6 +1261,15 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
 		if (data != 0)
 			goto unhandled;
 		break;
+	case MSR_IA32_DEBUGCTLMSR:
+		svm->vmcb->save.dbgctl = data;
+		if (!svm_has(SVM_FEATURE_LBRV))
+			break;
+		if (data & (1ULL<<0))
+			svm_enable_lbrv(svm);
+		else
+			svm_disable_lbrv(svm);
+		break;
 	default:
 	unhandled:
 		return kvm_set_msr_common(vcpu, ecx, data);
-- 
1.5.3.7




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Re: [PATCH 3/3] KVM: SVM: enable LBRV virtualization

[Avi Kivity]

Joerg Roedel wrote:
> @@ -1224,6 +1261,15 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
>  		if (data != 0)
>  			goto unhandled;
>  		break;
> +	case MSR_IA32_DEBUGCTLMSR:
> +		svm->vmcb->save.dbgctl = data;
> +		if (!svm_has(SVM_FEATURE_LBRV))
> +			break;
> +		if (data & (1ULL<<0))
> +			svm_enable_lbrv(svm);
> +		else
> +			svm_disable_lbrv(svm);
> +		break;
>  	default:
>  	unhandled:
>  		return kvm_set_msr_common(vcpu, ecx, data);
>   

This still has the same issue as the previous patchset:  if the guest 
enables some other bit in MSR_IA32_DEBUCTLMSR, we silently ignore it.  
We should either pr_unimpl() on such bits or not handle them (ultimately 
injecting a #GP).

Also, I'd like a simple patch for 2.6.25 to add support for Windows x86 
on AMD.  So if the first patch in the series can add support for the 
bits that Windows sets in MSR_IA32_DEBUGCTLMSR (I imagine it just writes 
zero?) then I can queue that for 2.6.25 and the rest for 2.6.26.

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Re: [PATCH 3/3] KVM: SVM: enable LBRV virtualization

[Joerg Roedel]

On Wed, Feb 13, 2008 at 11:50:58AM +0200, Avi Kivity wrote:
> Joerg Roedel wrote:
> >@@ -1224,6 +1261,15 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
> > 		if (data != 0)
> > 			goto unhandled;
> > 		break;
> >+	case MSR_IA32_DEBUGCTLMSR:
> >+		svm->vmcb->save.dbgctl = data;
> >+		if (!svm_has(SVM_FEATURE_LBRV))
> >+			break;
> >+		if (data & (1ULL<<0))
> >+			svm_enable_lbrv(svm);
> >+		else
> >+			svm_disable_lbrv(svm);
> >+		break;
> > 	default:
> > 	unhandled:
> > 		return kvm_set_msr_common(vcpu, ecx, data);
> >  
> 
> This still has the same issue as the previous patchset:  if the guest enables some other bit 
> in MSR_IA32_DEBUCTLMSR, we silently ignore it.  We should either pr_unimpl() on such bits or 
> not handle them (ultimately injecting a #GP).

Thats not true. The patch saves the MSR value in vmcb->save.dbgctl. This
value is returned on reads of that MSR. So no bit is ignored. This value
in the VMCB is also used as the guests copy of that MSR if LBR
virtualization is enabled. But another issue, I should ensure the guest
does not set reserved bits in that MSR.

> Also, I'd like a simple patch for 2.6.25 to add support for Windows x86 on AMD.  So if the 
> first patch in the series can add support for the bits that Windows sets in 
> MSR_IA32_DEBUGCTLMSR (I imagine it just writes zero?) then I can queue that for 2.6.25 and 
> the rest for 2.6.26.

Ok, I will work that into the patchset.

Joerg

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Re: [PATCH 3/3] KVM: SVM: enable LBRV virtualization

[Avi Kivity]

Joerg Roedel wrote:
>>>  
>>>       
>> This still has the same issue as the previous patchset:  if the guest enables some other bit 
>> in MSR_IA32_DEBUCTLMSR, we silently ignore it.  We should either pr_unimpl() on such bits or 
>> not handle them (ultimately injecting a #GP).
>>     
>
> Thats not true. The patch saves the MSR value in vmcb->save.dbgctl. This
> value is returned on reads of that MSR. So no bit is ignored. This value
> in the VMCB is also used as the guests copy of that MSR if LBR
> virtualization is enabled. 

Right, my mistake.

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Re: KVM: SVM: Implement LBRV virtualization

[Maciej Kowalczyk]

On Tue, 12 Feb 2008 16:27:07 +0100, Joerg Roedel <joerg.roedel@amd.com>  
wrote:
> This little patchset implements virtualization of the Last Branch Record
> feature (LBRV) into the KVM-AMD module where this is available in  
> hardware. For
> every non-LBRV capable hardware it only enables access to the 5 LBR  
> MSRs. Without
> this access Windows XP 64 bit crashes in the installation routine.

Does it mean that it's impossible to install Windows XP x64 on older AMD  
processors under KVM?
Or maybe just newer models crashed during install?

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Re: KVM: SVM: Implement LBRV virtualization

[Joerg Roedel]

On Tue, Feb 12, 2008 at 04:53:44PM +0100, Maciej Kowalczyk wrote:
> On Tue, 12 Feb 2008 16:27:07 +0100, Joerg Roedel <joerg.roedel@amd.com> wrote:
> >This little patchset implements virtualization of the Last Branch Record
> >feature (LBRV) into the KVM-AMD module where this is available in hardware. For
> >every non-LBRV capable hardware it only enables access to the 5 LBR MSRs. Without
> >this access Windows XP 64 bit crashes in the installation routine.
> 
> Does it mean that it's impossible to install Windows XP x64 on older AMD processors under KVM?
> Or maybe just newer models crashed during install?
> 
>

Installation of XP 64 bit should work now on every AMD system which has
support for KVM. The critical point here was the access to the MSRs.
These MSRs are virtualized in newer AMD processors (Fam10h) and
therefore I implemented this feature in this patchset too.

Joerg

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Re: KVM: SVM: Implement LBRV virtualization

[Alexey Eremenko]

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Hi all,

Can you explain a bit more about "LBRV virtualization" or give links, that explain this ?

-Alexey "Technologov"

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[-- Attachment #2: Type: text/plain, Size: 228 bytes --]

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Re: KVM: SVM: Implement LBRV virtualization

[Joerg Roedel]

On Tue, Feb 12, 2008 at 08:35:50AM -0800, Alexey Eremenko wrote:
> 
> Hi all,
> 
> Can you explain a bit more about "LBRV virtualization" or give links, that explain this ?

LBRV stands for Last Branch Record Virtualization. The LBR consists
basically of 4 MSRs: The RIPs of the last branch (from and to RIP) and the
RIPs of the last exception (from and to RIP). The recording of these
MSRs need to enabled in a fifth MSR (DEBUG_CTL). On K8 with SVM the
guest has no own copys of these MSRs. On Barcelona, there is a new SVM
feature which gives the guest its own copies of these MSRs. This needs
to be enabled setting lbr_ctl to 1 in the VMCB. If this is done, the
hardware switches to the guest copies of these MSRs when doing a VMRUN.
You can find more details about this in the AMD Architecture Programmers
Manual Volume 2, Section 15.22.
My patch only enables LBRV if the guest enables Last Branch Recording in
its copy of the DEBUG_CTL MSR.

Joerg

-- 
           |           AMD Saxony Limited Liability Company & Co. KG
 Operating |         Wilschdorfer Landstr. 101, 01109 Dresden, Germany
 System    |                  Register Court Dresden: HRA 4896
 Research  |              General Partner authorized to represent:
 Center    |             AMD Saxony LLC (Wilmington, Delaware, US)
           | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy



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