[patch 2/3] QEMU/KVM: ACPI PCI hotplug multiple bus support

[Marcelo Tosatti <mtosatti@redhat.com>]

[-- Attachment #1: hotplug-support --]
[-- Type: text/plain, Size: 4863 bytes --]

Support more than one bus in the ACPI PCI hotplug code.

Currently 4 buses are supported, but can be easily extended.

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>

Index: kvm-userspace.pci3/qemu/hw/acpi.c
===================================================================
--- kvm-userspace.pci3.orig/qemu/hw/acpi.c
+++ kvm-userspace.pci3/qemu/hw/acpi.c
@@ -552,10 +552,11 @@ struct gpe_regs {
 struct pci_status {
     uint32_t up;
     uint32_t down;
+    unsigned long base;
 };
 
 static struct gpe_regs gpe;
-static struct pci_status pci0_status;
+static struct pci_status pci_bus_status[4];
 
 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 {
@@ -625,16 +626,19 @@ static void gpe_writeb(void *opaque, uin
 
 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 {
-    uint32_t val = 0;
     struct pci_status *g = opaque;
-    switch (addr) {
-        case PCI_BASE:
+    uint32_t val, offset;
+
+    offset = addr - g->base;
+    switch (offset) {
+        case 0:
             val = g->up;
             break;
-        case PCI_BASE + 4:
+        case 4:
             val = g->down;
             break;
         default:
+            val = 0;
             break;
     }
 
@@ -647,11 +651,13 @@ static uint32_t pcihotplug_read(void *op
 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 {
     struct pci_status *g = opaque;
-    switch (addr) {
-        case PCI_BASE:
+    uint32_t offset = addr - g->base;
+
+    switch (offset) {
+        case 0:
             g->up = val;
             break;
-        case PCI_BASE + 4:
+        case 4:
             g->down = val;
             break;
    }
@@ -671,9 +677,13 @@ static uint32_t pciej_read(void *opaque,
 
 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 {
-    int slot = ffs(val) - 1;
+    struct pci_status *g = opaque;
+    int slot, bus;
 
-    device_hot_remove_success(0, slot);
+    bus = (g->base - PCI_BASE) / 12;
+    slot = ffs(val) - 1;
+
+    device_hot_remove_success(bus, slot);
 
 #if defined(DEBUG)
     printf("pciej write %lx <== %d\n", addr, val);
@@ -684,17 +694,25 @@ static const char *model;
 
 void qemu_system_hot_add_init(const char *cpu_model)
 {
+    int i;
+
     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 
     register_ioport_write(PROC_BASE, 4, 1, gpe_writeb, &gpe);
     register_ioport_read(PROC_BASE, 4, 1,  gpe_readb, &gpe);
 
-    register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
-    register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
+    for (i = 0; i < 4; i++) {
+        struct pci_status *pci_status = &pci_bus_status[i];
+        unsigned long base = PCI_BASE + (i*12);
+
+        pci_status->base = base;
+        register_ioport_write(base, 8, 4, pcihotplug_write, pci_status);
+        register_ioport_read(base, 8, 4,  pcihotplug_read, pci_status);
+        register_ioport_write(base+8, 4, 4, pciej_write, pci_status);
+        register_ioport_read(base+8, 4, 4,  pciej_read, pci_status);
+    }
 
-    register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL);
-    register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, NULL);
 
     model = cpu_model;
 }
@@ -740,28 +758,34 @@ void qemu_system_cpu_hot_add(int cpu, in
 }
 #endif
 
-static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
+static void enable_device(struct pci_status *p, struct gpe_regs *g, int bus, int slot)
 {
-    g->sts |= 2;
-    g->en |= 2;
+    int gpe_bit = (1 << (bus+1));
+
+    g->sts |= gpe_bit;
+    g->en |= gpe_bit;
     p->up |= (1 << slot);
 }
 
-static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
+static void disable_device(struct pci_status *p, struct gpe_regs *g, int bus, int slot)
 {
-    g->sts |= 2;
-    g->en |= 2;
+    int gpe_bit = (1 << (bus+1));
+
+    g->sts |= gpe_bit;
+    g->en |= gpe_bit;
     p->down |= (1 << slot);
 }
 
 void qemu_system_device_hot_add(int pcibus, int slot, int state)
 {
+    struct pci_status *pci_status = &pci_bus_status[pcibus];
+
     qemu_set_irq(pm_state->irq, 1);
-    pci0_status.up = 0;
-    pci0_status.down = 0;
+    pci_status->up = 0;
+    pci_status->down = 0;
     if (state)
-        enable_device(&pci0_status, &gpe, slot);
+        enable_device(pci_status, &gpe, pcibus, slot);
     else
-        disable_device(&pci0_status, &gpe, slot);
+        disable_device(pci_status, &gpe, pcibus, slot);
     qemu_set_irq(pm_state->irq, 0);
 }

-- 


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