From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcelo Tosatti Subject: Re: [RFC]RE: [PATCH] kvm-ia64 irq assignment 1/2 kernel Date: Wed, 11 Jun 2008 13:02:34 -0300 Message-ID: <20080611160234.GA3659@dmt.cnet> References: <51CFAB8CB6883745AE7B93B3E084EBE201CC875F@pdsmsx412.ccr.corp.intel.com> <484996EE.8060600@qumranet.com> <51CFAB8CB6883745AE7B93B3E084EBE201CC8A14@pdsmsx412.ccr.corp.intel.com> <64146E7D-9E1E-4ED2-9682-14C05E1A9B0E@suse.de> <51CFAB8CB6883745AE7B93B3E084EBE201CC8A61@pdsmsx412.ccr.corp.intel.com> <6D2233ED-090D-4B6B-A305-838DDCEB3CD7@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: "Xu, Anthony" , Avi Kivity , Jes Sorensen , kvm@vger.kernel.org, kvm-ia64@vger.kernel.org To: Alexander Graf Return-path: Received: from mx1.redhat.com ([66.187.233.31]:50823 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753693AbYFKQD1 (ORCPT ); Wed, 11 Jun 2008 12:03:27 -0400 Content-Disposition: inline In-Reply-To: <6D2233ED-090D-4B6B-A305-838DDCEB3CD7@suse.de> Sender: kvm-owner@vger.kernel.org List-ID: On Wed, Jun 11, 2008 at 07:24:09AM -0700, Alexander Graf wrote: > > On Jun 10, 2008, at 12:57 AM, Xu, Anthony wrote: > >> Thanks for comments >> >> Basically we are on the same page, while I didn't find your patch about >> irq assignment, can you post it in this thread again, thx? > > I'll attach it to this mail. > >> Below patch makes all PCI devices use level-trigger , active low >> interrupt, it worked well when running linux guest, I didn't try windows >> guest yet. >> (didn't have windows image in hand) >> >> Please comment! >> >> If this is acceptabled, we can figure out how to use IOAPIC in kvm/ia32 >> based on this. Which will reduce irq sharing dramatically. >> >> >> Thanks, >> Anthony >> >> >> >> diff --git a/bios/acpi-dsdt.dsl b/bios/acpi-dsdt.dsl >> index 21fc76a..4b5e824 100755 >> --- a/bios/acpi-dsdt.dsl >> +++ b/bios/acpi-dsdt.dsl >> @@ -974,7 +974,7 @@ DefinitionBlock ( >> Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link >> Name(_UID, 1) >> Name(_PRS, ResourceTemplate(){ >> - Interrupt (, Level, ActiveHigh, Shared) >> + Interrupt (, Level, ActiveLow, Shared) > > This looks pretty much correct to me ;-). You might also want to add the > GSI functionality I have in my patch. The only thing we have not discussed > so far is, how do interrupts get routed when _PIC is not set to 1, aka the > "boot case"? Hi Alexander, Anthony, I think it would be better to avoid static PCI pin -> IOAPIC pin assignments, if PCI link devices can be used (allowing the OS to route IRQ's as it wishes to). Take a look at http://www.microsoft.com/whdc/archive/acpi-mp.mspx. It seems cleaner to use "bimodal link nodes" (using the parlance from URL above) instead of "bimodal _PRT" as your present GSI patch is using. My current inclination is: - Move the PCI interrupt link device code to a method in a separate file (with arguments such as _UID, IRQ list, etc). - Create separate PCI interrupt link devices for each PCI pin of each slot (see the example table at end of URL). - Assign all available IRQ's covered by the single IOAPIC (0-24) in the interrupt list for these interrupt link devices. I'll try Anthony's patch with Windows.