[PATCH] kvm-ia64 irq assignment 2/2 userspace

[PATCH] kvm-ia64 irq assignment 2/2 userspace

[Xu, Anthony]

In kvm-ia64, PCI devices use 48-pin virtual IOAPIC to deliver interrup.


Signed-off-by: Anthony Xu < anthony.xu@intel.com >

diff --git a/qemu/hw/piix_pci.c b/qemu/hw/piix_pci.c
index 90cb3a6..797ece7 100644
--- a/qemu/hw/piix_pci.c
+++ b/qemu/hw/piix_pci.c
@@ -28,6 +28,7 @@

 typedef uint32_t pci_addr_t;
 #include "pci_host.h"
+#include "qemu-kvm.h"

 typedef PCIHostState I440FXState;

@@ -51,6 +52,11 @@ static void piix3_set_irq(qemu_irq *pic, int irq_num,
int level);
 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
 {
     int slot_addend;
+#if defined(KVM_CAP_IRQCHIP) && defined(TARGET_IA64)
+    int dev;
+    dev = pci_dev->devfn >> 3;
+    return (((((dev) << 2) + ((dev) >> 3) + (irq_num)) & 31) + 16);
+#endif
     slot_addend = (pci_dev->devfn >> 3) - 1;
     return (irq_num + slot_addend) & 3;
 }
@@ -171,12 +177,18 @@ static int i440fx_load(QEMUFile* f, void *opaque,
int version_id)

 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
 {
+    int nirq;
     PCIBus *b;
     PCIDevice *d;
     I440FXState *s;

+#if defined(KVM_CAP_IRQCHIP) && defined(TARGET_IA64)
+    nirq = 48;
+#else
+    nirq = 4;
+#endif
     s = qemu_mallocz(sizeof(I440FXState));
-    b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
+    b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, pic, 0,
nirq);
     s->bus = b;

     register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
@@ -220,6 +232,11 @@ static void piix3_set_irq(qemu_irq *pic, int
irq_num, int level)
 {
     int i, pic_irq, pic_level;

+#if defined(KVM_CAP_IRQCHIP) && defined(TARGET_IA64)
+    if(kvm_enabled())
+        kvm_set_irq(irq_num, level);
+    return;
+#endif
     pci_irq_levels[irq_num] = level;

     /* now we change the pic irq level according to the piix irq
mappings */
 

Re: [PATCH] kvm-ia64 irq assignment 2/2 userspace

[Marcelo Tosatti]

On Fri, Jun 06, 2008 at 11:59:02PM +0800, Xu, Anthony wrote:
> In kvm-ia64, PCI devices use 48-pin virtual IOAPIC to deliver interrup.
> 
> 
> Signed-off-by: Anthony Xu < anthony.xu@intel.com >
> 
> diff --git a/qemu/hw/piix_pci.c b/qemu/hw/piix_pci.c
> index 90cb3a6..797ece7 100644
> --- a/qemu/hw/piix_pci.c
> +++ b/qemu/hw/piix_pci.c
> @@ -28,6 +28,7 @@
> 
>  typedef uint32_t pci_addr_t;
>  #include "pci_host.h"
> +#include "qemu-kvm.h"
> 
>  typedef PCIHostState I440FXState;
> 
> @@ -51,6 +52,11 @@ static void piix3_set_irq(qemu_irq *pic, int irq_num,
> int level);
>  static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
>  {
>      int slot_addend;
> +#if defined(KVM_CAP_IRQCHIP) && defined(TARGET_IA64)
> +    int dev;
> +    dev = pci_dev->devfn >> 3;
> +    return (((((dev) << 2) + ((dev) >> 3) + (irq_num)) & 31) + 16);
> +#endif
>      slot_addend = (pci_dev->devfn >> 3) - 1;
>      return (irq_num + slot_addend) & 3;
>  }

You don't support -no-kvm-irqchip on IA64? 

Also, cosmetically would be nicer to create a separate get_pirq function
for IA64.

> @@ -171,12 +177,18 @@ static int i440fx_load(QEMUFile* f, void *opaque,
> int version_id)
> 
>  PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
>  {
> +    int nirq;
>      PCIBus *b;
>      PCIDevice *d;
>      I440FXState *s;
> 
> +#if defined(KVM_CAP_IRQCHIP) && defined(TARGET_IA64)
> +    nirq = 48;
> +#else
> +    nirq = 4;
> +#endif
>      s = qemu_mallocz(sizeof(I440FXState));
> -    b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
> +    b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, pic, 0,
> nirq);
>      s->bus = b;

This should be dynamic if possible. Don't want another ifdef for when x86 
routes through IOAPIC.

>      register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
> @@ -220,6 +232,11 @@ static void piix3_set_irq(qemu_irq *pic, int
> irq_num, int level)
>  {
>      int i, pic_irq, pic_level;
> 
> +#if defined(KVM_CAP_IRQCHIP) && defined(TARGET_IA64)
> +    if(kvm_enabled())
> +        kvm_set_irq(irq_num, level);
> +    return;
> +#endif
>      pci_irq_levels[irq_num] = level;

Why the current hook into i8259_set_irq does not work for IA64? 

I think this breaks interrupt sharing, because the logic to detect if
all devices sharing the line are low or high is in i8259_set_irq, and
you simply skip that.

Re: [PATCH] kvm-ia64 irq assignment 2/2 userspace

[Marcelo Tosatti]

> > @@ -220,6 +232,11 @@ static void piix3_set_irq(qemu_irq *pic, int
> > irq_num, int level)
> >  {
> >      int i, pic_irq, pic_level;
> > 
> > +#if defined(KVM_CAP_IRQCHIP) && defined(TARGET_IA64)
> > +    if(kvm_enabled())
> > +        kvm_set_irq(irq_num, level);
> > +    return;
> > +#endif
> >      pci_irq_levels[irq_num] = level;
> 
> Why the current hook into i8259_set_irq does not work for IA64? 

    if (pic_irq < 16) {
        /* The pic level is the logical OR of all the PCI irqs mapped
           to it */

Ok, but still, how can you share interrupts by directly changing the
level without checking for individual devices first.

> I think this breaks interrupt sharing, because the logic to detect if
> all devices sharing the line are low or high is in i8259_set_irq, and

s/i8259_set_irq/piix3_set_irq/

> you simply skip that.