From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcelo Tosatti Subject: Re: [RFC]RE: [PATCH] kvm-ia64 irq assignment 1/2 kernel Date: Sat, 14 Jun 2008 19:58:21 -0300 Message-ID: <20080614225821.GA22724@dmt.cnet> References: <51CFAB8CB6883745AE7B93B3E084EBE201CC875F@pdsmsx412.ccr.corp.intel.com> <484996EE.8060600@qumranet.com> <51CFAB8CB6883745AE7B93B3E084EBE201CC8A14@pdsmsx412.ccr.corp.intel.com> <64146E7D-9E1E-4ED2-9682-14C05E1A9B0E@suse.de> <51CFAB8CB6883745AE7B93B3E084EBE201CC8A61@pdsmsx412.ccr.corp.intel.com> <6D2233ED-090D-4B6B-A305-838DDCEB3CD7@suse.de> <20080611160234.GA3659@dmt.cnet> <51CFAB8CB6883745AE7B93B3E084EBE201CC9071@pdsmsx412.ccr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Alexander Graf , Avi Kivity , Jes Sorensen , kvm@vger.kernel.org, kvm-ia64@vger.kernel.org To: "Xu, Anthony" Return-path: Received: from mx1.redhat.com ([66.187.233.31]:45131 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756543AbYFNW6r (ORCPT ); Sat, 14 Jun 2008 18:58:47 -0400 Content-Disposition: inline In-Reply-To: <51CFAB8CB6883745AE7B93B3E084EBE201CC9071@pdsmsx412.ccr.corp.intel.com> Sender: kvm-owner@vger.kernel.org List-ID: On Fri, Jun 13, 2008 at 12:15:23AM +0800, Xu, Anthony wrote: > > I think it would be better to avoid static PCI pin -> IOAPIC pin > > assignments, if PCI link devices can be used (allowing the OS to route > > IRQ's as it wishes to). > Seems PCI link device only support irq-pin < 16, > IOAPIC pin 16~23 can not be used. > > > > > > > Take a look at http://www.microsoft.com/whdc/archive/acpi-mp.mspx. It > > seems cleaner to use "bimodal link nodes" (using the parlance from URL > > above) instead of "bimodal _PRT" as your present GSI patch is using. > Bimodal _PRT is a great idea, I never thought of it before, thanks. > > While in PIIX platform there are only 4 PCI link entries, how can we > introduce more? Where to put these added entries? > still in ISA bridge configure space. Would have to write an ACPI-IOAPIC "IRQ router" to replace PIIX. It would be queried via a SystemIO region, so QEMU can know what IRQ has been assigned to a particular slot/func (OS can then change IRQ assignment via link device _SRS method). That seems to be necessary for dynamic IRQ assignment of slots/function once you have more than one IOAPIC (note we can also assign one IRQ to each function inside each slot, currently there's one IRQ per _slot_). > Another concern is, can this link use irq-pin > 15? > In the example ASL code in the web page you provided, they use irq-pin > <=15 Sure it can, as long as the OS has notified its not using PIIX's PIC (via the _PIC method).