From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcelo Tosatti Subject: Re: [patch 0/7] force the TSC unreliable by reporting C2 state Date: Wed, 18 Jun 2008 19:41:18 -0300 Message-ID: <20080618224118.GA23236@dmt.cnet> References: <20080618164205.108219607@localhost.localdomain> <48596B85.7090008@codemonkey.ws> <20080618204042.GA15981@dmt.cnet> <485977EF.3090002@codemonkey.ws> <20080618212106.GA19602@dmt.cnet> <48598150.604@codemonkey.ws> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Avi Kivity , kvm@vger.kernel.org, John Stultz , "Yang, Sheng" To: Anthony Liguori Return-path: Received: from mx1.redhat.com ([66.187.233.31]:43361 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753990AbYFRWmA (ORCPT ); Wed, 18 Jun 2008 18:42:00 -0400 Content-Disposition: inline In-Reply-To: <48598150.604@codemonkey.ws> Sender: kvm-owner@vger.kernel.org List-ID: On Wed, Jun 18, 2008 at 04:42:40PM -0500, Anthony Liguori wrote: > Marcelo Tosatti wrote: >> On Wed, Jun 18, 2008 at 04:02:39PM -0500, Anthony Liguori wrote: >> >>>>> Have we yet determined why the TSC is so unstable in the first >>>>> place? In theory, it should be relatively stable on single-node >>>>> Intel and Barcelona chips. >>>>> >>>> If the host enters C2/C3, or changes CPU frequency, it becomes >>>> unreliable as a clocksource and there's no guarantee the guest will >>>> detect that. >>>> >>> On Intel, the TSC should be fixed-frequency for basically all >>> shipping processors supporting VT. Starting with 10h (Barcelona), I >>> believe AMD also has a fixed frequency TSC. >>> >> >> But still stops ticking in C2/C3 state, I suppose? >> > > I don't know for sure but the TSC is not tied to the CPU clock so I > would be surprised if it did. I think that that would defeat the > utility of a fixed-frequency TSC. Well, Linux assumes that TSC stops ticking on C2/C3. Section 18.10 of Intel says: "The specific processor configuration determines the behavior. Constant TSC behavior ensures that the duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if the processor core changes frequency. This is the architectural behavior moving forward." However it does not mention C2/C3. Could someone confirm either way?