From: Alex Chiang <achiang@hp.com>
To: "Zhao, Yu" <yu.zhao@intel.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>,
linux-pci@vger.kernel.org, Randy Dunlap <randy.dunlap@oracle.com>,
Greg KH <greg@kroah.com>,
Grant Grundler <grundler@parisc-linux.org>,
Matthew Wilcox <matthew@wil.cx>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
virtualization@lists.linux-foundation.org,
xen-devel@lists.xensource.com
Subject: Re: [PATCH 1/4 v2] PCI: introduce new base functions
Date: Wed, 10 Sep 2008 16:37:11 -0600 [thread overview]
Message-ID: <20080910223711.GA16740@ldl.fc.hp.com> (raw)
In-Reply-To: <7A25B56E4BE99C4283EB931CD1A40E110181CB4E@pdsmsx414.ccr.corp.intel.com>
* Zhao, Yu <yu.zhao@intel.com>:
>
> It can be PCI_BRIDGE_RESOURCES, because there may be some
> non-standard resources following PCI_ROM_RESOURCE and before
> PCI_BRIDGE_RESOURCES.
>
> For example, a standard PCI device has following resources:
> 0 - 5 BARs
> 6 ROM
> 7 - 10 Bridge
>
> After SR-IOV is enabled, it becomes
> 0 - 5 standard BARs
> 6 Rom
> 7 - 12 SR-IOV BARs
> 13 - 16 Bridge
Ok, makes sense now; was that documented somewhere else, and I
just missed it?
> Same as above, the PCI_BRIDGE_RES_END varies when some features
> is enabled or disabled.
Ok, I must have missed this documentation too.
> Thank you very much for carefully reviewing these patches. I'd
> like to invite you to review next version again if it's
> convenient for you.
Sure, you can Cc me next time too.
Thanks.
/ac
prev parent reply other threads:[~2008-09-10 22:38 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-09-01 11:20 [PATCH 1/4 v2] PCI: introduce new base functions Zhao, Yu
2008-09-01 16:15 ` Alex Chiang
2008-09-10 8:17 ` Zhao, Yu
2008-09-10 22:37 ` Alex Chiang [this message]
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