From: Sheng Yang <sheng@linux.intel.com>
To: Zwane Mwaikambo <zwane@infradead.org>
Cc: Avi Kivity <avi@redhat.com>,
kvm@vger.kernel.org, Alex Williamson <alex.williamson@hp.com>
Subject: Re: [PATCH 4/4] kvm: bios: switch MTRRs to cover only the PCI range and default to WB
Date: Sun, 28 Sep 2008 09:58:05 +0800 [thread overview]
Message-ID: <200809280958.05388.sheng@linux.intel.com> (raw)
In-Reply-To: <alpine.DEB.2.00.0809270653460.24433@montezuma.windriver.com>
On Saturday 27 September 2008 21:55:33 Zwane Mwaikambo wrote:
> On Sat, 27 Sep 2008, Avi Kivity wrote:
> > Yang, Sheng wrote:
> > > I think we should do a little more than just write msr to update mtrr.
> > >
> > > Intel SDM 10.11.8 "MTRR consideration in MP Systems" define the
> > > procedure to modify MTRR msr in MP. Especially, step 4 enter no-fill
> > > cache mode(set CR0.CD bit and clean NW bit), step 12 re-enabled the
> > > caching(clear this two bits).
> > >
> > > We based on these behaviors to detect MTRR update.
> >
> > Why not simply flush the mmu on an mtrr write?
> >
> > (though of course I have no objection to doing what the manual says)
>
> Detecting that condition is fine for operating systems which follow it,
> but some don't, including older Linux kernels :( Flushing on MTRR write,
> although being overzealous would be the most robust.
OK, this trade off is reasonable, I will update the mtrr patch.
Hope we won't got problem in so early stage. :)
--
regards
Yang, Sheng
prev parent reply other threads:[~2008-09-28 1:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-09-25 17:52 [PATCH 4/4] kvm: bios: switch MTRRs to cover only the PCI range and default to WB Alex Williamson
2008-09-27 5:35 ` Yang, Sheng
2008-09-27 13:36 ` Avi Kivity
2008-09-27 13:55 ` Zwane Mwaikambo
2008-09-28 1:58 ` Sheng Yang [this message]
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