From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sheng Yang Subject: Re: [PATCH 4/4] kvm: bios: switch MTRRs to cover only the PCI range and default to WB Date: Sun, 28 Sep 2008 09:58:05 +0800 Message-ID: <200809280958.05388.sheng@linux.intel.com> References: <1222365149.8138.266.camel@2710p.home> <48DE36C1.4070700@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Cc: Avi Kivity , kvm@vger.kernel.org, Alex Williamson To: Zwane Mwaikambo Return-path: Received: from mga06.intel.com ([134.134.136.21]:31670 "EHLO orsmga101.jf.intel.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751824AbYI1B5Q (ORCPT ); Sat, 27 Sep 2008 21:57:16 -0400 In-Reply-To: Content-Disposition: inline Sender: kvm-owner@vger.kernel.org List-ID: On Saturday 27 September 2008 21:55:33 Zwane Mwaikambo wrote: > On Sat, 27 Sep 2008, Avi Kivity wrote: > > Yang, Sheng wrote: > > > I think we should do a little more than just write msr to update mtrr. > > > > > > Intel SDM 10.11.8 "MTRR consideration in MP Systems" define the > > > procedure to modify MTRR msr in MP. Especially, step 4 enter no-fill > > > cache mode(set CR0.CD bit and clean NW bit), step 12 re-enabled the > > > caching(clear this two bits). > > > > > > We based on these behaviors to detect MTRR update. > > > > Why not simply flush the mmu on an mtrr write? > > > > (though of course I have no objection to doing what the manual says) > > Detecting that condition is fine for operating systems which follow it, > but some don't, including older Linux kernels :( Flushing on MTRR write, > although being overzealous would be the most robust. OK, this trade off is reasonable, I will update the mtrr patch. Hope we won't got problem in so early stage. :) -- regards Yang, Sheng