From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Yang, Sheng" Subject: Re: Remaining passthrough/VT-d tasks list Date: Sun, 28 Sep 2008 13:17:53 +0800 Message-ID: <200809281317.53842.sheng.yang@intel.com> References: <0122C7C995D32147B66BF4F440D3016301C49E61@pdsmsx415.ccr.corp.intel.com> <48DF1046.1050102@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: 7bit Cc: "Tian, Kevin" , "Han, Weidong" , "kvm@vger.kernel.org" , Amit Shah , "benami@il.ibm.com" , "muli@il.ibm.com" , "Kay, Allen M" , "Zhang, Xiantao" To: Avi Kivity Return-path: Received: from mga02.intel.com ([134.134.136.20]:55957 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751110AbYI1FRE (ORCPT ); Sun, 28 Sep 2008 01:17:04 -0400 In-Reply-To: <48DF1046.1050102@redhat.com> Content-Disposition: inline Sender: kvm-owner@vger.kernel.org List-ID: On Sunday 28 September 2008 13:04:06 Avi Kivity wrote: > Tian, Kevin wrote: > >> No. Maybe the Neocleus polarity trick (which also reduces performance). > > > > To my knowledge, Neocleus polarity trick can't solve this isolation > > issue, which just provides one effecient way to track > > assertion/deassertion transition on the irq line. For example, reverse > > polarity when receiving an instance, and then a new irq instance would > > occur when all devices de- assert on shared irq line, and then recover > > the polarity. In your concerned case where guest driver misbehaves, this > > polarity trick can't work neither as one device always asserts the line. > > You're right, I didn't think it through. > > If there was a standard way to mask pci irqs, it might have worked, but > there isn't, unfortunately. > What if we got a way to mask pci irqs? We also have to unmask pci irq when guest wrote EOI to vlapic(or at any other time). I think this still cause problem. The problem is, we don't know if guest would deassert the line. Maybe add some time-based detection here might work? And about the mask of pci irq, how about disable PCI device interrupt using Device Control Register bit 10? Not sure if it would affect the pending transaction, also not sure all device support this (though they should support). -- regards Yang, Sheng