From: "Yang, Sheng" <sheng.yang@intel.com>
To: Jan Kiszka <jan.kiszka@siemens.com>
Cc: "kvm-devel" <kvm@vger.kernel.org>
Subject: Re: LAPIC soft-disable vs. LVT masking
Date: Mon, 20 Oct 2008 17:46:35 +0800 [thread overview]
Message-ID: <200810201746.35506.sheng.yang@intel.com> (raw)
In-Reply-To: <48FC4607.10803@siemens.com>
On Monday 20 October 2008 16:49:11 Jan Kiszka wrote:
> Hi Sheng,
>
> obviously, I meditated too long over the APIC specs and VAPIC code of
> KVM: When the guest resets the soft-enable bit in SVR, the in-kernel
> APIC implementation also set the LVT masked bits - so far, so fine
> (according to specs). But I failed to read out of that doc if those mask
> bits are permanently set (until the guest clears them again) or only
> until the soft-disabling ends (ie. they are restored to their previous
> state - QEMU goes this way). Can you clarify?
>
> Thanks,
> Jan
>
Hi Jan
I also can't find related info in the spec. But I think, when software enable
bit is cleaned, the spec said the mask bits are set, which means the content
of register is changed. And no words for what happen if set software enable
bit, so I think it maybe retain the mask state after software enable (a
little more possibility).
I will give a update if I got more infos.
--
regards
Yang, Sheng
next prev parent reply other threads:[~2008-10-20 9:48 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-10-20 8:49 LAPIC soft-disable vs. LVT masking Jan Kiszka
2008-10-20 9:46 ` Yang, Sheng [this message]
2008-10-20 11:31 ` Sheng Yang
2008-10-20 11:58 ` Jan Kiszka
2008-10-20 12:16 ` Sheng Yang
2008-10-20 12:21 ` Jan Kiszka
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