From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sheng Yang Subject: Re: [PATCH 6/7] KVM: Split IOAPIC structure Date: Fri, 9 Jan 2009 13:55:55 +0800 Message-ID: <200901091355.56110.sheng@linux.intel.com> References: <1231411535-2461-1-git-send-email-sheng@linux.intel.com> <1231411535-2461-7-git-send-email-sheng@linux.intel.com> <20090108152721.GA5391@amt.cnet> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Cc: Avi Kivity , kvm@vger.kernel.org To: Marcelo Tosatti Return-path: Received: from mga09.intel.com ([134.134.136.24]:1891 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752735AbZAIFz7 (ORCPT ); Fri, 9 Jan 2009 00:55:59 -0500 In-Reply-To: <20090108152721.GA5391@amt.cnet> Content-Disposition: inline Sender: kvm-owner@vger.kernel.org List-ID: On Thursday 08 January 2009 23:27:21 Marcelo Tosatti wrote: > On Thu, Jan 08, 2009 at 06:45:34PM +0800, Sheng Yang wrote: > > Prepared for reuse ioapic_redir_entry for MSI. > > What is the disadvantage of dispatching the MSI interrupts to the vcpus > via the IOAPIC? Pin shortage I can think of, but adding more IOAPIC's is > possible (and wanted anyway for systems with insane amounts of net/block > devices). > > That would avoid code duplication (might need to handle a few msi > specific bits). I think for current RH=1 implement, independence of IOAPIC is acceptable... Indicated by "Redicection hint indication"(RH) bit, there are two mode that MSI would deliver: either use IOAPIC redirect table entry(RH=0), or redirect directly(RH=1). I implemented the later for now, and it's the most common way. Of course, delivery would go through IOAPIC when RH=0. -- regards Yang, Sheng