From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joerg Roedel Subject: Re: [PATCH 4/6] kvm/x86/mmu: handle invlpg on large pages Date: Fri, 6 Mar 2009 14:06:05 +0100 Message-ID: <20090306130605.GH8751@amd.com> References: <1236255153-4432-1-git-send-email-joerg.roedel@amd.com> <1236255153-4432-5-git-send-email-joerg.roedel@amd.com> <20090305211122.GA5660@amt.cnet> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Avi Kivity , kvm@vger.kernel.org, linux-kernel@vger.kernel.org To: Marcelo Tosatti Return-path: Received: from outbound-sin.frontbridge.com ([207.46.51.80]:52448 "EHLO SG2EHSOBE003.bigfish.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751175AbZCFNGo convert rfc822-to-8bit (ORCPT ); Fri, 6 Mar 2009 08:06:44 -0500 Content-Disposition: inline In-Reply-To: <20090305211122.GA5660@amt.cnet> Sender: kvm-owner@vger.kernel.org List-ID: On Thu, Mar 05, 2009 at 06:11:22PM -0300, Marcelo Tosatti wrote: > On Thu, Mar 05, 2009 at 01:12:31PM +0100, Joerg Roedel wrote: > > Signed-off-by: Joerg Roedel > > --- > > arch/x86/kvm/paging_tmpl.h | 12 +++++++++--- > > 1 files changed, 9 insertions(+), 3 deletions(-) > >=20 > > diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.= h > > index 79668ba..aa79396 100644 > > --- a/arch/x86/kvm/paging_tmpl.h > > +++ b/arch/x86/kvm/paging_tmpl.h > > @@ -441,6 +441,7 @@ out_unlock: > > static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) > > { > > struct kvm_shadow_walk_iterator iterator; > > + struct kvm_mmu_page *sp; > > pt_element_t gpte; > > gpa_t pte_gpa =3D -1; > > int level; > > @@ -451,12 +452,17 @@ static void FNAME(invlpg)(struct kvm_vcpu *vc= pu, gva_t gva) > > for_each_shadow_entry(vcpu, gva, iterator) { > > level =3D iterator.level; > > sptep =3D iterator.sptep; > > + sp =3D page_header(__pa(sptep)); > > + > > + if (sp->role.direct) { > > + /* mapped from a guest's large_pte */ > > + kvm_mmu_zap_page(vcpu->kvm, sp); > > + kvm_flush_remote_tlbs(vcpu->kvm); > > + return; > > + } >=20 > If the guest has 32-bit pte's there might be: >=20 > - two large shadow entries to cover 4MB > - one large shadow entry and one shadow page with 512 4k entries > - two shadow pages with 512 4k entries each >=20 > So need to cover all this cases. Right. Thanks for pointing this out. I will post an updated version of this patch. Joerg --=20 | Advanced Micro Devices GmbH Operating | Karl-Hammerschmidt-Str. 34, 85609 Dornach bei M=C3=BCnchen System |=20 Research | Gesch=C3=A4ftsf=C3=BChrer: Jochen Polster, Thomas M. McCoy= , Giuliano Meroni Center | Sitz: Dornach, Gemeinde Aschheim, Landkreis M=C3=BCnchen | Registergericht M=C3=BCnchen, HRB Nr. 43632