From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH v12 1/8] PCI: initialize and release SR-IOV capability Date: Thu, 26 Mar 2009 15:50:48 -0700 Message-ID: <20090326155048.4a8f9d36@hobbes> References: <1237519518-24048-1-git-send-email-yu.zhao@intel.com> <1237519518-24048-2-git-send-email-yu.zhao@intel.com> <20090320105409.5ed80885@hobbes.lan> <20090321140511.GA24964@yzhao-otc.sh.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: "linux-pci@vger.kernel.org" , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" To: Yu Zhao Return-path: In-Reply-To: <20090321140511.GA24964@yzhao-otc.sh.intel.com> Sender: linux-pci-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On Sat, 21 Mar 2009 22:05:11 +0800 Yu Zhao wrote: > On Sat, Mar 21, 2009 at 01:54:09AM +0800, Jesse Barnes wrote: > > On Fri, 20 Mar 2009 11:25:11 +0800 > > Yu Zhao wrote: > > > > > If a device has the SR-IOV capability, initialize it (set the ARI > > > Capable Hierarchy in the lowest numbered PF if necessary; > > > calculate the System Page Size for the VF MMIO, probe the VF > > > Offset, Stride and BARs). A lock for the VF bus allocation is > > > also initialized if a PF is the lowest numbered PF. > > > > > > Reviewed-by: Matthew Wilcox > > > Signed-off-by: Yu Zhao > > > > I applied this series to my linux-next branch, but there were a few > > conflicts here and there, so please check it out. Looks like from > > start to finish this took about 6 months to get banged into shape, > > thanks for staying on it, Yu! > > Yes, I checked them and found there is conflict between the SR-IOV > changes and Yinghai's 'PCI/x86: detect host bridge config space size > w/o using quirks'. Following is the fix, thanks! > > > New pci_cfg_space_size() needs invalid pdev->class, put it in the > right place in the pci_setup_device(). > > Signed-off-by: Yu Zhao Applied, thanks Yu. -- Jesse Barnes, Intel Open Source Technology Center