From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joerg Roedel Subject: Re: [PATCH 2/6] MMU: don't bail on PAT bits in PTE Date: Fri, 15 May 2009 15:19:43 +0200 Message-ID: <20090515131943.GT9835@amd.com> References: <1242375740-31222-1-git-send-email-agraf@suse.de> <1242375740-31222-2-git-send-email-agraf@suse.de> <1242375740-31222-3-git-send-email-agraf@suse.de> <20090515102507.GA4933@redhat.com> <44CC74E2-96C3-45C6-9412-A252A53C966A@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: "Michael S. Tsirkin" , kvm@vger.kernel.org To: Alexander Graf Return-path: Received: from outbound-dub.frontbridge.com ([213.199.154.16]:53614 "EHLO IE1EHSOBE004.bigfish.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763024AbZEONTz convert rfc822-to-8bit (ORCPT ); Fri, 15 May 2009 09:19:55 -0400 Content-Disposition: inline In-Reply-To: <44CC74E2-96C3-45C6-9412-A252A53C966A@suse.de> Sender: kvm-owner@vger.kernel.org List-ID: On Fri, May 15, 2009 at 12:53:42PM +0200, Alexander Graf wrote: > > On 15.05.2009, at 12:25, Michael S. Tsirkin wrote: > >> On Fri, May 15, 2009 at 10:22:16AM +0200, Alexander Graf wrote: >>> A 64bit PTE can have bit7 set to 1 which means "Use this bit for th= e=20 >>> PAT". >>> Currently KVM's MMU code treats this bit as reserved, even though =20 >>> it's not. >>> >>> As long as we're not required to make use of the PAT bits which is = =20 >>> only >>> required for DMA/MMIO from my understanding, we can safely ignore i= t. >>> >>> Hyper-V uses this bit for kernel PTEs. >>> >>> Signed-off-by: Alexander Graf >>> --- >>> arch/x86/kvm/mmu.c | 2 +- >>> 1 files changed, 1 insertions(+), 1 deletions(-) >>> >>> diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c >>> index 8fcdae9..cce055a 100644 >>> --- a/arch/x86/kvm/mmu.c >>> +++ b/arch/x86/kvm/mmu.c >>> @@ -2169,7 +2169,7 @@ static void reset_rsvds_bits_mask(struct =20 >>> kvm_vcpu *vcpu, int level) >>> context->rsvd_bits_mask[1][1] =3D exb_bit_rsvd | >>> rsvd_bits(maxphyaddr, 51) | >>> rsvd_bits(13, 20); /* large page */ >>> - context->rsvd_bits_mask[1][0] =3D ~0ull; >>> + context->rsvd_bits_mask[1][0] =3D 0ull; >>> break; >>> } >>> } >> >> Just to make sure I understand what this does: if guest sets bit7, =20 >> will >> bit7 get set in shadow PTEs as well? > > I don't see any code that interprets bit7, so the shadow PTE should b= e =20 > completely unaffected. > > But to be sure I asked J=F6rg to take a look at it as well, as he's m= ore =20 > familiar with the x86 SPT code than I am :-). The PAT bit is not propagated into the shadow page tables. Anyway, the problem is fixed the wrong way in this patch. The real problem is that = a 4kb pte is checked with mask considered for large pages (which do not exist on walker level 0). The attached patch fixes it the better way imho. =46rom 7530aef3ed580b70a74224f8c04857754501c496 Mon Sep 17 00:00:00 200= 1 =46rom: Joerg Roedel Date: Fri, 15 May 2009 15:14:19 +0200 Subject: [PATCH] kvm/mmu: fix reserved bit checking on 4kb pte level The reserved bits checking code looks at bit 7 of the pte to determine if it has to use the mask for a large pte or a normal pde. This does no= t work on 4kb pte level because bit 7 is used there for PAT. Account this in the checking function. Signed-off-by: Joerg Roedel --- arch/x86/kvm/mmu.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 479e748..8d9552e 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -2124,9 +2124,11 @@ static void paging_free(struct kvm_vcpu *vcpu) =20 static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int leve= l) { - int bit7; + int bit7 =3D 0; + + if (level !=3D PT_PAGE_TABLE_LEVEL) + bit7 =3D (gpte >> 7) & 1; =20 - bit7 =3D (gpte >> 7) & 1; return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) !=3D 0; } =20 --=20 1.6.2.4 --=20 | Advanced Micro Devices GmbH Operating | Karl-Hammerschmidt-Str. 34, 85609 Dornach bei M=FCnchen System |=20 Research | Gesch=E4ftsf=FChrer: Thomas M. McCoy, Giuliano Meroni Center | Sitz: Dornach, Gemeinde Aschheim, Landkreis M=FCnchen | Registergericht M=FCnchen, HRB Nr. 43632