From mboxrd@z Thu Jan  1 00:00:00 1970
From: Joerg Roedel <joerg.roedel@amd.com>
Subject: Re: [PATCH 3/3] KVM: Cache pdptrs
Date: Tue, 2 Jun 2009 11:30:43 +0200
Message-ID: <20090602093043.GO4062@amd.com>
References: <1243862524-22120-1-git-send-email-avi@redhat.com> <1243862524-22120-4-git-send-email-avi@redhat.com> <20090602090428.GN4062@amd.com> <4A24EC3D.9020507@redhat.com>
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Cc: kvm@vger.kernel.org, Marcelo Tosatti <mtosatti@redhat.com>,
	Sheng Yang <sheng@linux.intel.com>
To: Avi Kivity <avi@redhat.com>
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On Tue, Jun 02, 2009 at 12:09:17PM +0300, Avi Kivity wrote:
> Joerg Roedel wrote:
>> On Mon, Jun 01, 2009 at 04:22:03PM +0300, Avi Kivity wrote:
>>  =20
>>> +static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
>>> +{
>>> +	switch (reg) {
>>> +	case VCPU_EXREG_PDPTR:
>>> +		BUG_ON(!npt_enabled);
>>> +		load_pdptrs(vcpu, vcpu->arch.cr3);
>>> +		break;
>>> +	default:
>>> +		BUG();
>>> +	}
>>> +}
>>>    =20
>>
>> Don't we need to check for the return value of load_pdptrs() here an=
d inject
>> a #GP it it fails?
>>  =20
>
> We're after some random exit, the guest won't be expecting a #GP in s=
ome =20
> random instruction.
>
> The only options are ignore and triple fault.

Thats not different from PAE with NPT anyways. With NPT the hardware
does not load all four pdptrs on cr3 switch time, only when they
are used.

Joerg

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