From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jamie Lokier Subject: Re: [Qemu-devel] [PATCH] Inter-VM shared memory PCI device Date: Tue, 9 Mar 2010 19:00:30 +0000 Message-ID: <20100309190030.GB11042@shareable.org> References: <1267833161-25267-1-git-send-email-cam@cs.ualberta.ca> <201003072254.00040.paul@codesourcery.com> <20100308014537.GA24024@shareable.org> <201003081304.45862.paul@codesourcery.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: qemu-devel@nongnu.org, Cam Macdonell , kvm@vger.kernel.org To: Paul Brook Return-path: Received: from mail2.shareable.org ([80.68.89.115]:57596 "EHLO mail2.shareable.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754320Ab0CITAh (ORCPT ); Tue, 9 Mar 2010 14:00:37 -0500 Content-Disposition: inline In-Reply-To: <201003081304.45862.paul@codesourcery.com> Sender: kvm-owner@vger.kernel.org List-ID: Paul Brook wrote: > > However, coherence could be made host-type-independent by the host > > mapping and unampping pages, so that each page is only mapped into one > > guest (or guest CPU) at a time. Just like some clustering filesystems > > do to maintain coherence. > > You're assuming that a TLB flush implies a write barrier, and a TLB miss > implies a read barrier. I'd be surprised if this were true in general. The host driver itself can issue full barriers at the same time as it maps pages on TLB miss, and would probably have to interrupt the guest's SMP KVM threads to insert a full barrier when broadcasting a TLB flush on unmap. -- Jamie