From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] Inter-VM shared memory PCI device Date: Wed, 10 Mar 2010 00:03:38 +0000 Message-ID: <201003100003.38612.paul@codesourcery.com> References: <1267833161-25267-1-git-send-email-cam@cs.ualberta.ca> <201003081303.45179.paul@codesourcery.com> <20100309201243.GH11042@shareable.org> Mime-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Cc: qemu-devel@nongnu.org, Cam Macdonell , Avi Kivity , kvm@vger.kernel.org To: Jamie Lokier Return-path: Received: from mail.codesourcery.com ([38.113.113.100]:44800 "EHLO mail.codesourcery.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751565Ab0CJADo (ORCPT ); Tue, 9 Mar 2010 19:03:44 -0500 In-Reply-To: <20100309201243.GH11042@shareable.org> Sender: kvm-owner@vger.kernel.org List-ID: > > In a cross environment that becomes extremely hairy. For example the x86 > > architecture effectively has an implicit write barrier before every > > store, and an implicit read barrier before every load. > > Btw, x86 doesn't have any implicit barriers due to ordinary loads. > Only stores and atomics have implicit barriers, afaik. As of March 2009[1] Intel guarantees that memory reads occur in order (they may only be reordered relative to writes). It appears AMD do not provide this guarantee, which could be an interesting problem for heterogeneous migration.. Paul [*] The most recent docs I have handy. Up to and including Core-2 Duo.