From: Marcelo Tosatti <mtosatti@redhat.com>
To: Xiao Guangrong <xiaoguangrong@cn.fujitsu.com>
Cc: Avi Kivity <avi@redhat.com>, Sheng Yang <sheng@linux.intel.com>,
LKML <linux-kernel@vger.kernel.org>,
KVM list <kvm@vger.kernel.org>
Subject: Re: [PATCH v3] KVM MMU: check reserved bits only if CR4.PSE=1 or CR4.PAE=1
Date: Tue, 23 Mar 2010 12:32:01 -0300 [thread overview]
Message-ID: <20100323153201.GA16878@amt.cnet> (raw)
In-Reply-To: <4BA34ADD.9040903@cn.fujitsu.com>
On Fri, Mar 19, 2010 at 05:58:53PM +0800, Xiao Guangrong wrote:
> - Check reserved bits only if CR4.PAE=1 or CR4.PSE=1 when guest #PF occurs
> - Fix a typo in reset_rsvds_bits_mask()
>
> Signed-off-by: Xiao Guangrong <xiaoguangrong@cn.fujitsu.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
> ---
> arch/x86/kvm/mmu.c | 12 +++++++++---
> 1 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
> index b137515..d6c1f03 100644
> --- a/arch/x86/kvm/mmu.c
> +++ b/arch/x86/kvm/mmu.c
> @@ -2293,13 +2293,19 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
> /* no rsvd bits for 2 level 4K page table entries */
> context->rsvd_bits_mask[0][1] = 0;
> context->rsvd_bits_mask[0][0] = 0;
> + context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
> +
> + if (!is_pse(vcpu)) {
> + context->rsvd_bits_mask[1][1] = 0;
> + break;
> + }
> +
> if (is_cpuid_PSE36())
> /* 36bits PSE 4MB page */
> context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
> else
> /* 32 bits PSE 4MB page */
> context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
> - context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
> break;
> case PT32E_ROOT_LEVEL:
> context->rsvd_bits_mask[0][2] =
> @@ -2312,7 +2318,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
> context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
> rsvd_bits(maxphyaddr, 62) |
> rsvd_bits(13, 20); /* large page */
> - context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
> + context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
> break;
> case PT64_ROOT_LEVEL:
> context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
> @@ -2330,7 +2336,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
> context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
> rsvd_bits(maxphyaddr, 51) |
> rsvd_bits(13, 20); /* large page */
> - context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
> + context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
> break;
> }
> }
> --
> 1.6.6.1
next prev parent reply other threads:[~2010-03-23 16:13 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-03-19 9:58 [PATCH v3] KVM MMU: check reserved bits only if CR4.PSE=1 or CR4.PAE=1 Xiao Guangrong
2010-03-23 15:32 ` Marcelo Tosatti [this message]
2010-03-24 9:25 ` Avi Kivity
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20100323153201.GA16878@amt.cnet \
--to=mtosatti@redhat.com \
--cc=avi@redhat.com \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=sheng@linux.intel.com \
--cc=xiaoguangrong@cn.fujitsu.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox