From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gleb Natapov Subject: Re: [PATCH] KVM: VMX: Translate interrupt shadow when waiting on NMI window Date: Wed, 21 Apr 2010 18:30:15 +0300 Message-ID: <20100421153015.GG14124@redhat.com> References: <20100216101705.GG2995@redhat.com> <4B7A72FB.8020709@siemens.com> <20100216103235.GH2995@redhat.com> <4B7A755B.80009@siemens.com> <20100216103816.GI2995@redhat.com> <4BCF08DF.8060709@siemens.com> <20100421143007.GE14124@redhat.com> <4BCF0EA2.3010100@siemens.com> <20100421144401.GF14124@redhat.com> <4BCF163C.8060408@siemens.com> Mime-Version: 1.0 Content-Type: text/plain; charset=cp1255 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Avi Kivity , Marcelo Tosatti , kvm To: Jan Kiszka Return-path: Received: from mx1.redhat.com ([209.132.183.28]:30479 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753777Ab0DUPaV convert rfc822-to-8bit (ORCPT ); Wed, 21 Apr 2010 11:30:21 -0400 Content-Disposition: inline In-Reply-To: <4BCF163C.8060408@siemens.com> Sender: kvm-owner@vger.kernel.org List-ID: On Wed, Apr 21, 2010 at 05:14:04PM +0200, Jan Kiszka wrote: > Gleb Natapov wrote: > > On Wed, Apr 21, 2010 at 04:41:38PM +0200, Jan Kiszka wrote: > >> Gleb Natapov wrote: > >>> On Wed, Apr 21, 2010 at 04:17:03PM +0200, Jan Kiszka wrote: > >>>> Gleb Natapov wrote: > >>>>> On Tue, Feb 16, 2010 at 11:37:15AM +0100, Jan Kiszka wrote: > >>>>>> Gleb Natapov wrote: > >>>>>>> On Tue, Feb 16, 2010 at 11:27:07AM +0100, Jan Kiszka wrote: > >>>>>>>> Gleb Natapov wrote: > >>>>>>>>> On Tue, Feb 16, 2010 at 11:14:45AM +0100, Jan Kiszka wrote: > >>>>>>>>>> Gleb Natapov wrote: > >>>>>>>>>>> On Tue, Feb 16, 2010 at 11:04:10AM +0100, Jan Kiszka wrot= e: > >>>>>>>>>>>> Gleb Natapov wrote: > >>>>>>>>>>>>> On Tue, Feb 16, 2010 at 10:16:12AM +0100, Jan Kiszka wr= ote: > >>>>>>>>>>>>>> Found while browsing Xen code: While we assume that th= e STI interrupt > >>>>>>>>>>>>>> shadow also inplies virtual NMI blocking, some process= ors may have a > >>>>>>>>>>>>>> different opinion (SDM 3: 22.3). To avoid misunderstan= dings that would > >>>>>>>>>>>>>> cause endless VM entry attempts, translate STI into MO= V SS blocking when > >>>>>>>>>>>>>> requesting the NMI window. > >>>>>>>>>>>>>> > >>>>>>>>>>>>> Why not just remove "block by STI" check in vmx_nmi_all= owed()? IIRC this > >>>>>>>>>>>>> is documented that on some CPUs STI does not block NMI. > >>>>>>>>>>>>> > >>>>>>>>>>>> Probably because we will stumble and fall on those CPUs = that do care. > >>>>>>>>>>>> > >>>>>>>>>>> But this defines behaviour of cpu _we_ emulate. So on _ou= r_ cpu NMI will > >>>>>>>>>>> not be blocked by STI. > >>>>>>>>>> The host CPU decides if it accepts an NMI injections while > >>>>>>>>> Are you sure? I haven't found such check during VMENTRY. > >>>>>>>> I also only find the explicitly stated exclusion of MOV SS b= locking vs. > >>>>>>>> NMI injection. If we can rely on this, removing STI blocking= from > >>>>>>>> vmx_nmi_allowed should suffice. Or, better, can we get an of= ficial > >>>>>>>> confirmation from Intel? > >>>>>>>> > >>>>>>> SDM 2b says about STI instruction: > >>>>>>> The IF flag and the STI and CLI instructions do not prohibit = the > >>>>>>> generation of exceptions and NMI interrupts. NMI interrupts (= and SMIs) > >>>>>>> may be blocked for one macroinstruction following an STI. > >>>>>> Yes, it's likely that this is the architectural reason for the= delayed > >>>>>> NMI window signaling after STI. Still, we are looking for the > >>>>>> entry-check logic. > >>>>>> > >>>>> Will ask Intel. > >>>>> > >>>> Just remembered that there was some open topic... Did your ask? = Any answer? > >>>> > >>> I did and got answer last week :) The answer is that NMI is block= ed only > >>> if GUEST_INTR_STATE_NMI flag is set. MOV SS and STI shouldn't blo= ck NMI, > >>> so vmx_nmi_allowed() should check only GUEST_INTR_STATE_NMI flag. > >> Cool, that's now increasing my level of confusion again: :( > >> > >> Thought we only wanted to confirm that it's still safe to inject N= MIs > >> when blocked-by-STI is set. Now we hear that it's also safe when M= OV SS > >> is active? That would directly contradict the SDM (at least the ve= rsion > >> I have at hand: June 2009). Or did I misunderstand the answer? > >> > > No you don't. I was told that software should be prepared to handle= NMI > > after MOV SS. What part of SDM does this contradict? I found nothin= g in > > latest SDM. >=20 > [ updated to March 2010 version ] >=20 > To sum up the scenario again, I think it started with >=20 > =95 If the =93NMI-window exiting=94 VM-execution control is 1, a VM e= xit occurs before > execution of any instruction if there is no virtual-NMI blocking an= d there is no > blocking of events by MOV SS (see Table 21-3). (A logical processor= may also > prevent such a VM exit if there is blocking of events by STI.) Such= a VM exit > occurs immediately after VM entry if the above conditions are true = (see Section > 23.6.6). >=20 >=20 > We included STI into the NMI shadow, but we /may/ get early exits on > some processors according to the statement above. According to your > latest info, we can also get that when the MOV SS shadow is on!? But > simply allowing NMI injection under MOV SS is not possible: >=20 > 23.3 CHECKING AND LOADING GUEST STATE > 23.3.1.5 Checks on Guest Non-Register State >=20 > =95 Interruptibility state. > ... > =97 Bit 1 (blocking by MOV-SS) must be 0 if the valid bit (bit 31) = in the VM-entry > interruption-information field is 1 and the interruption type (bi= ts 10:8) in that > field has value 2, indicating non-maskable interrupt (NMI). >=20 >=20 > And doing this for STI sounds risky too: >=20 > =97 A processor may require bit 0 (blocking by STI) to be 0 if the = valid bit (bit 31) > in the VM-entry interruption-information field is 1 and the inter= ruption type > (bits 10:8) in that field has value 2, indicating NMI. Other proc= essors may not > make this requirement. >=20 >=20 > Should we start stepping over the shadow like we do for svm? >=20 If x86 ISA allows NMI to be injected after STI and MOV SS we can clear blocking by STI/MOV SS bits before injecting NMI. But why would Intel add those checks then. Will ask Intel once again. Hope will get respons= e sooner now. > [ There should be a law that requires hardware builders to write > software according to their own manuals... ] >=20 +1 -- Gleb.