From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sheng Yang Subject: Re: [PATCH v2] KVM VMX: Make sure single type invvpid is supported before issuing invvpid instruction Date: Thu, 3 Jun 2010 17:58:50 +0800 Message-ID: <201006031758.50792.sheng@linux.intel.com> References: <4C076B72.1030308@cn.fujitsu.com> <201006031657.02854.sheng@linux.intel.com> <4C0779B2.8000001@cn.fujitsu.com> Mime-Version: 1.0 Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: Avi Kivity , kvm@vger.kernel.org To: Gui Jianfeng Return-path: Received: from mga10.intel.com ([192.55.52.92]:24528 "EHLO fmsmga102.fm.intel.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753440Ab0FCM4z (ORCPT ); Thu, 3 Jun 2010 08:56:55 -0400 In-Reply-To: <4C0779B2.8000001@cn.fujitsu.com> Sender: kvm-owner@vger.kernel.org List-ID: On Thursday 03 June 2010 17:45:22 Gui Jianfeng wrote: > According to SDM, we need check whether single-context INVVPID type is > supported before issuing invvpid instruction. > > Signed-off-by: Gui Jianfeng > --- > arch/x86/include/asm/vmx.h | 2 ++ > arch/x86/kvm/vmx.c | 14 +++++++++++++- > 2 files changed, 15 insertions(+), 1 deletions(-) > > diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h > index 104cf86..4e78b25 100644 > --- a/arch/x86/include/asm/vmx.h > +++ b/arch/x86/include/asm/vmx.h > @@ -376,6 +376,8 @@ enum vmcs_field { > #define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25) > #define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26) > > +#define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) > + > #define VMX_EPT_DEFAULT_GAW 3 > #define VMX_EPT_MAX_GAW 0x4 > #define VMX_EPT_MT_EPTE_SHIFT 3 > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c > index 0e561a5..f363fe3 100644 > --- a/arch/x86/kvm/vmx.c > +++ b/arch/x86/kvm/vmx.c > @@ -355,6 +355,17 @@ static inline bool cpu_has_vmx_invept_global(void) > return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; > } > > +static inline bool cpu_has_vmx_invvpid_single(void) > +{ > + /* > + * bit 41 of IA32_VMX_EPT_VPID_CAP MSR indicates whehter the > + * single-context INVVPID type is supported. vmx_capability.vpid > + * represents the higher 32 bits of IA32_VMX_EPT_VPID_CAP MSR, so > + * VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT(bit 9) is used here. > + */ The comment is better with the VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT marco, since it would also applied to other similar ones. And I have checked my sent mail, found the word "later" maybe the reason you put the comment here... In fact I meant something like #define VMX_EPT_INVVPID_SINGLE_CONTEXT_BIT (1 << 9) /* (41 - 32) */ Sorry if the word caused confusing... -- regards Yang, Sheng > + return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; > +} > + > static inline bool cpu_has_vmx_ept(void) > { > return vmcs_config.cpu_based_2nd_exec_ctrl & > @@ -499,7 +510,8 @@ static inline void vpid_sync_vcpu_all(struct vcpu_vmx > *vmx) if (vmx->vpid == 0) > return; > > - __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); > + if (cpu_has_vmx_invvpid_single()) > + __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); > } > > static inline void ept_sync_global(void)