From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Michael S. Tsirkin" Subject: Re: Mask bit support's API Date: Tue, 23 Nov 2010 14:04:16 +0200 Message-ID: <20101123120416.GB26313@redhat.com> References: <201011231409.52666.sheng.yang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Avi Kivity , Marcelo Tosatti , kvm@vger.kernel.org To: "Yang, Sheng" Return-path: Received: from mx1.redhat.com ([209.132.183.28]:12361 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751187Ab0KWMEa (ORCPT ); Tue, 23 Nov 2010 07:04:30 -0500 Content-Disposition: inline In-Reply-To: <201011231409.52666.sheng.yang@intel.com> Sender: kvm-owner@vger.kernel.org List-ID: On Tue, Nov 23, 2010 at 02:09:52PM +0800, Yang, Sheng wrote: > Hi Avi, > > I've purposed the following API for mask bit support. > > The main point is, QEmu can know which entries are enabled(by pci_enable_msix()). Unfortunately, it can't I think, unless all your guests are linux. "enabled entries" is a linux kernel concept. The MSIX spec only tells you which entries are masked and which are unmasked. -- MST