From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Yang, Sheng" Subject: Re: Mask bit support's API Date: Tue, 23 Nov 2010 22:02:01 +0800 Message-ID: <201011232202.02050.sheng.yang@intel.com> References: <201011231409.52666.sheng.yang@intel.com> <20101123120416.GB26313@redhat.com> Mime-Version: 1.0 Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: Avi Kivity , Marcelo Tosatti , "kvm@vger.kernel.org" To: "Michael S. Tsirkin" Return-path: Received: from mga09.intel.com ([134.134.136.24]:22990 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752046Ab0KWOBd (ORCPT ); Tue, 23 Nov 2010 09:01:33 -0500 In-Reply-To: <20101123120416.GB26313@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: On Tuesday 23 November 2010 20:04:16 Michael S. Tsirkin wrote: > On Tue, Nov 23, 2010 at 02:09:52PM +0800, Yang, Sheng wrote: > > Hi Avi, > > > > I've purposed the following API for mask bit support. > > > > The main point is, QEmu can know which entries are enabled(by > > pci_enable_msix()). > > Unfortunately, it can't I think, unless all your guests are linux. > "enabled entries" is a linux kernel concept. > The MSIX spec only tells you which entries are masked and which are > unmasked. Can't understand what you are talking about, and how it related to the guest OS. I was talking about pci_enable_msix() in the host Linux. -- regards Yang, Sheng