From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gleb Natapov Subject: Re: [PATCH kvm-unit-tests 2/4] Introduce a C++ wrapper for the kvm APIs Date: Wed, 24 Nov 2010 18:48:45 +0200 Message-ID: <20101124164845.GC20014@redhat.com> References: <1290595933-13122-1-git-send-email-avi@redhat.com> <1290595933-13122-3-git-send-email-avi@redhat.com> <50DD1E97-0ECD-41E6-B6F8-1D78AA4A4876@suse.de> <4CED2416.1040102@codemonkey.ws> <20101124154006.GE15111@redhat.com> <4CED344B.3030000@codemonkey.ws> <20101124161204.GF15111@redhat.com> <4CED39DE.3030207@redhat.com> <20101124162153.GA20014@redhat.com> <4CED40CD.8030503@codemonkey.ws> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Avi Kivity , Alexander Graf , Marcelo Tosatti , kvm@vger.kernel.org To: Anthony Liguori Return-path: Received: from mx1.redhat.com ([209.132.183.28]:15859 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754937Ab0KXQsu (ORCPT ); Wed, 24 Nov 2010 11:48:50 -0500 Content-Disposition: inline In-Reply-To: <4CED40CD.8030503@codemonkey.ws> Sender: kvm-owner@vger.kernel.org List-ID: On Wed, Nov 24, 2010 at 10:43:57AM -0600, Anthony Liguori wrote: > On 11/24/2010 10:21 AM, Gleb Natapov wrote: > >On Wed, Nov 24, 2010 at 06:14:22PM +0200, Avi Kivity wrote: > >>On 11/24/2010 06:12 PM, Gleb Natapov wrote: > >>>> Why would we specify a PIIX3 device based on a configuration file? > >>>> There is only one PIIX3 device in the world. I don't see a lot of > >>>> need to create arbitrary types of devices. > >>>> > >>>Why deny this flexibility from those who need it for modelling > >>>different HW? > >>The various components exist and can be reused. > >> > >So you are saying lets use code as data for some and config files for > >others. If you have support for building chipsets from data why not > >simply have 440fx.cfg somewhere? Besides what qemu provides no is not > >stock PIIX3. We have parts of PIIX4 for power management. > > > >>>Besides, as I said, PIIX3 is ISA bridge and this > >>>is what class should implement. > >>Isn't it an ISA bridge + a few ISA devices? > >> > >Why? Because they happen to be on the same silicon? So then in SoC > >all devices are in cpu? > > They *aren't* ISA devices. Look at the PIIX3 spec. All of the > ports for these devices are positively decoded and not sent over the > ISA bus. > Over the external ISA bus you mean? > You could model them as being behind the ISA bus but you could also > model them as being behind the PCI bus. > Just yesterday I checked how different ports behave if you use inw/inl to read data from them. They behave very different from what PCI spec says. This was recent HW. -- Gleb.