From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Roedel, Joerg" Subject: Re: [PATCH 0/9] KVM: Make the instruction emulator aware of Nested Virtualization Date: Tue, 30 Nov 2010 09:47:53 +0100 Message-ID: <20101130084753.GF2258@amd.com> References: <1290622715-8382-1-git-send-email-joerg.roedel@amd.com> <4CED63DC.20608@redhat.com> <20101125114640.GC6031@amd.com> <20101125131351.GA9382@amd.com> <4CEE7E21.3060007@redhat.com> <20101125162313.GA9411@amd.com> <11557.1291051418@localhost> <20101129183212.GD15575@8bytes.org> <18726.1291060870@localhost> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Cc: Joerg Roedel , Avi Kivity , Marcelo Tosatti , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" To: "Valdis.Kletnieks@vt.edu" Return-path: Content-Disposition: inline In-Reply-To: <18726.1291060870@localhost> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On Mon, Nov 29, 2010 at 03:01:10PM -0500, Valdis.Kletnieks@vt.edu wrote: > On Mon, 29 Nov 2010 19:32:12 +0100, Joerg Roedel said: > > On Mon, Nov 29, 2010 at 12:23:38PM -0500, Valdis.Kletnieks@vt.edu wrote: > > > (Sorry for late reply...) > > > > > > On Thu, 25 Nov 2010 17:23:13 +0100, "Roedel, Joerg" said: > > > > On Thu, Nov 25, 2010 at 10:17:53AM -0500, Avi Kivity wrote: > > > > > On 11/25/2010 03:13 PM, Roedel, Joerg wrote: > > > > > What about things like adding instructions and forgetting to add the > > > > > corresponding svm.c code? > > > > Cannot happen. Every instruction that can be intercepted with SVM is > > > > already handled in this patch-set. > > > > > > Call us back when Intel releases the i9 and i11 with new instructions > > > that need intercept handling. ;) > > > > How does that affect SVM? > > It will quite possibly include instructions that can be intercepted with SVM > that are not in this patch set. At which point Joerg's comment can apply - it > will be possible to add it in one place and forget to add it in the svm.c code. SVM is AMD-only. So if an instruction does not exist on AMD there will also be no specific intercept for it. For newly added instructions to the AMD ISA which can then be intercepted I have to do bringup work anyway. This will include adding these intercepts to the code in this patch-set. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo, Andrew Bowd Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632