From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcelo Tosatti Subject: Re: [PATCH] qemu-kvm-x86: consider the irq0override flag in kvm_arch_init_irq_routing Date: Mon, 7 Feb 2011 08:12:59 -0200 Message-ID: <20110207101259.GA20825@amt.cnet> References: <1284472300-4211-1-git-send-email-bernhard.kohl@nsn.com> <4D4FBE7E.8090308@siemens.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Bernhard Kohl , kvm@vger.kernel.org To: Jan Kiszka Return-path: Received: from mx1.redhat.com ([209.132.183.28]:13078 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752277Ab1BGKNT (ORCPT ); Mon, 7 Feb 2011 05:13:19 -0500 Content-Disposition: inline In-Reply-To: <4D4FBE7E.8090308@siemens.com> Sender: kvm-owner@vger.kernel.org List-ID: On Mon, Feb 07, 2011 at 10:42:22AM +0100, Jan Kiszka wrote: > Hi Bernhard, > > On 2010-09-14 15:51, Bernhard Kohl wrote: > > The setting of the irq0override flag must be also passed properly > > to the KVM_IRQCHIP_IOAPIC. > > > > Signed-off-by: Bernhard Kohl > > --- > > qemu-kvm-x86.c | 4 ++-- > > 1 files changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/qemu-kvm-x86.c b/qemu-kvm-x86.c > > index fd974b3..e35c234 100644 > > --- a/qemu-kvm-x86.c > > +++ b/qemu-kvm-x86.c > > @@ -1388,9 +1388,9 @@ int kvm_arch_init_irq_routing(void) > > } > > } > > for (i = 0; i < 24; ++i) { > > - if (i == 0) { > > + if (i == 0 && irq0override) { > > r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, 2); > > - } else if (i != 2) { > > + } else if (i != 2 || !irq0override) { > > r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, i); > > } > > if (r < 0) { > > While cleaning up the irq0override fragments, I stumbled over this > commit. It is a nop for qemu-kvm, today and also by the time it was applied: > > irq0override = !kvm_irqchip || kvm_has_gsi_routing > > But, for obvious reasons, the code above is only executed when gsi > routing is available. > > Can you remember what motivated this patch? > > Jan Guest OS which can't cope with 0->2 GSI->IOAPIC pin mapping.