Re: [PATCH 0/5] perf support for amd guest/host-only bits v2

Paul Mackerras
2011-06-29T12:05:47Z

On Wed, Jun 29, 2011 at 11:02:54AM +0200, Peter Zijlstra wrote:
> On Tue, 2011-06-28 at 18:10 +0200, Joerg Roedel wrote:
> > On Fri, Jun 17, 2011 at 03:37:29PM +0200, Joerg Roedel wrote:
> > > this is the second version of the patch-set to support the AMD
> > > guest-/host only bits in the performance counter MSRs. Due to lack of
> > > time I havn't looked into emulating support for this feature on Intel or
> > > other architectures, but the other comments should be worked in. The
> > > changes to v1 include:
> > >
> > > * Rebased patches to v3.0-rc3
> > > * Allow exclude_guest and exclude_host set at the same time
> > > * Reworked event-parse logic for the new exclude-bits
> > > * Only count guest-events per default from perf-kvm
> >
> > Hi Peter, Ingo,
> >
> > have you had a chance to look at this patch-set? Are any changes
> > required?
>
> I would feel a lot more comfortable by having it implemented on all of
> x86 as well as at least one !x86 platform. Avi graciously volunteered
> for the Intel bits.
>
> Paulus, I hear from benh that you're also responsible for the ppc-kvm
> bits, could you possibly find some time to implement this feature for
> ppc?

I'll have a look at it, but I don't know how quickly I'll be able to
produce a patch.

We have two styles of KVM on PowerPC (at least as far as server
processors are concerned), one where the guest runs entirely in
usermode and the privileged facilities are emulated, and another that
uses hypervisor mode in the host and can allow the guest to use
supervisor mode. In the latter case, the PMU is considered a guest
resource, that is, the hardware allows the guest to manipulate the PMU
directly, and PMU interrupts go directly to the guest. In that mode
it's not really possible to count or profile guest activity from the
host. There are some hypervisor-only counters in the PMU but they
have limited event selection compared to the counters available to the
guest.

Paul.