Re: [Qemu-devel] [RFC v5 86/86] 440fx: fix PAM, PCI holes

Gleb Natapov
2011-07-25T13:36:01Z

On Mon, Jul 25, 2011 at 04:31:27PM +0300, Avi Kivity wrote:
> On 07/25/2011 04:28 PM, Avi Kivity wrote:
> >On 07/25/2011 04:17 PM, Gleb Natapov wrote:
> >>On Mon, Jul 25, 2011 at 04:14:45PM +0300, Avi Kivity wrote:
> >>> On 07/25/2011 04:07 PM, Anthony Liguori wrote:
> >>> >On 07/20/2011 11:50 AM, Avi Kivity wrote:
> >>> >>The current implementation of PAM and the PCI holes is
> >>broken in several
> >>> >>ways:
> >>> >>
> >>> >> - PCI BARs are not restricted to the PCI hole (a BAR may
> >>hide memory)
> >>> >
> >>> >Technically, a BAR can be mapped to any non-RAM memory location.
> >>>
> >>> I understood TOM (Top Of Memory) to be fixed - can't find a register
> >>> for it - but maybe I misread the spec.
> >>>
> >>PIIX3 spec:
> >>
> >>2.2.11. TOM—TOP OF MEMORY REGISTER (Function 0)
> >>Address Offset: 69h
> >>Default Value: 02h
> >>Attribute: Read/Write
> >>
> >
> >What's it doing in PIIX3? Is it the same TOM?
> >
>
> That's the ISA TOM (15MB hole and friends).
>
Correct. What about:
3.2.19. DRB[0:7] DRAM ROW BOUNDARY REGISTERS

from 440fx spec?

--
Gleb.