From mboxrd@z Thu Jan  1 00:00:00 1970
From: Gleb Natapov <gleb@redhat.com>
Subject: Re: [Qemu-devel] [RFC v5 86/86] 440fx: fix PAM, PCI holes
Date: Mon, 25 Jul 2011 16:31:24 +0300
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Cc: Anthony Liguori <anthony@codemonkey.ws>, qemu-devel@nongnu.org,
	kvm@vger.kernel.org
To: Avi Kivity <avi@redhat.com>
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On Mon, Jul 25, 2011 at 04:28:12PM +0300, Avi Kivity wrote:
> On 07/25/2011 04:17 PM, Gleb Natapov wrote:
> >On Mon, Jul 25, 2011 at 04:14:45PM +0300, Avi Kivity wrote:
> >>  On 07/25/2011 04:07 PM, Anthony Liguori wrote:
> >>  >On 07/20/2011 11:50 AM, Avi Kivity wrote:
> >>  >>The current implementation of PAM and the PCI holes is broken i=
n several
> >>  >>ways:
> >>  >>
> >>  >>    - PCI BARs are not restricted to the PCI hole (a BAR may hi=
de memory)
> >>  >
> >>  >Technically, a BAR can be mapped to any non-RAM memory location.
> >>
> >>  I understood TOM (Top Of Memory) to be fixed - can't find a regis=
ter
> >>  for it - but maybe I misread the spec.
> >>
> >PIIX3 spec:
> >
> >2.2.11.    TOM=97TOP OF MEMORY REGISTER (Function 0)
> >Address Offset:    69h
> >Default Value:     02h
> >Attribute:         Read/Write
> >
>=20
> What's it doing in PIIX3?  Is it the same TOM?
>=20
Good question. Looks like it is not:

This register enables the forwarding of ISA or DMA memory cycles to the
PCI Bus and sets the top of main
memory accessible by ISA or DMA devices. In addition, this register
controls the forwarding of ISA or DMA
accesses to the lower BIOS region (E0000=96EFFFFh) and the 512=96640-Kb=
yte
main memory region (80000=96
9FFFFh). The Top Of Memory configuration register must be set by the
BIOS.

--
			Gleb.